| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_ih.c | 71 ih->wptr_addr = dma_addr + ih->ring_size; in amdgpu_ih_ring_init()
98 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; in amdgpu_ih_ring_init()
134 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
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| A D | amdgpu_mes.h | 217 uint64_t wptr_addr; member
244 uint64_t wptr_addr; member
277 uint64_t wptr_addr; member
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| A D | cik_ih.c | 136 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in cik_ih_irq_init()
137 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cik_ih_irq_init()
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| A D | si_ih.c | 85 WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in si_ih_irq_init()
86 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in si_ih_irq_init()
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| A D | iceland_ih.c | 138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in iceland_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in iceland_ih_irq_init()
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| A D | cz_ih.c | 138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in cz_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cz_ih_irq_init()
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| A D | tonga_ih.c | 138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in tonga_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in tonga_ih_irq_init()
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| A D | amdgpu_ih.h | 62 uint64_t wptr_addr; member
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| A D | mes_v11_0.c | 338 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; in mes_v11_0_add_hw_queue()
340 mes_add_queue_pkt.wptr_addr = input->wptr_addr; in mes_v11_0_add_hw_queue()
493 mes_add_queue_pkt.wptr_addr = input->wptr_addr; in mes_v11_0_map_legacy_queue()
774 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; in mes_v11_0_reset_hw_queue()
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| A D | vega10_ih.c | 237 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in vega10_ih_enable_ring()
238 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in vega10_ih_enable_ring()
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| A D | vega20_ih.c | 273 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in vega20_ih_enable_ring()
274 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in vega20_ih_enable_ring()
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| A D | navi10_ih.c | 293 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in navi10_ih_enable_ring()
294 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in navi10_ih_enable_ring()
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| A D | ih_v6_0.c | 297 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in ih_v6_0_enable_ring()
298 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in ih_v6_0_enable_ring()
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| A D | ih_v6_1.c | 269 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in ih_v6_1_enable_ring()
270 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in ih_v6_1_enable_ring()
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| A D | ih_v7_0.c | 269 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in ih_v7_0_enable_ring()
270 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in ih_v7_0_enable_ring()
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| A D | amdgpu_mes.c | 301 queue_input.wptr_addr = ring->wptr_gpu_addr; in amdgpu_mes_map_legacy_queue()
353 queue_input.wptr_addr = ring->wptr_gpu_addr; in amdgpu_mes_reset_legacy_queue()
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| A D | mes_userqueue.c | 141 queue_input.wptr_addr = userq_props->wptr_gpu_addr; in mes_userq_map()
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| A D | mes_v12_0.c | 323 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; in mes_v12_0_add_hw_queue()
513 mes_add_queue_pkt.wptr_addr = input->wptr_addr; in mes_v12_0_map_legacy_queue()
865 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; in mes_v12_0_reset_hw_queue()
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| A D | gfx_v9_4_3.c | 204 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_4_3_kiq_map_queues() local
226 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx_v9_4_3_kiq_map_queues()
227 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx_v9_4_3_kiq_map_queues()
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| A D | gfx_v12_0.c | 311 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx_v12_0_kiq_map_queues() local
346 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx_v12_0_kiq_map_queues()
347 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx_v12_0_kiq_map_queues()
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| A D | gfx_v8_0.c | 4338 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx_v8_0_kiq_kcq_enable() local
4352 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx_v8_0_kiq_kcq_enable()
4353 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx_v8_0_kiq_kcq_enable()
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| A D | gfx_v11_0.c | 371 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx11_kiq_map_queues() local
406 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx11_kiq_map_queues()
407 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx11_kiq_map_queues()
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| A D | gfx_v9_0.c | 955 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx_v9_0_kiq_map_queues() local
977 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx_v9_0_kiq_map_queues()
978 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx_v9_0_kiq_map_queues()
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| /drivers/gpu/drm/amd/include/ |
| A D | mes_v11_api_def.h | 291 uint64_t wptr_addr; member
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| A D | mes_v12_api_def.h | 342 uint64_t wptr_addr; member
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