| /drivers/gpu/drm/amd/amdgpu/ |
| A D | mes_userqueue.c | 141 queue_input.wptr_addr = userq_props->wptr_gpu_addr; in mes_userq_map()
232 userq_props->wptr_gpu_addr = mqd_user->wptr_va; in mes_userq_mqd_create()
321 r = mes_userq_create_wptr_mapping(uq_mgr, queue, userq_props->wptr_gpu_addr); in mes_userq_mqd_create()
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| A D | amdgpu_mes.h | 174 uint64_t wptr_gpu_addr; member
184 uint64_t wptr_gpu_addr; member
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| A D | sdma_v4_0.c | 1095 u64 wptr_gpu_addr; in sdma_v4_0_gfx_resume() local
1141 wptr_gpu_addr = ring->wptr_gpu_addr; in sdma_v4_0_gfx_resume()
1143 lower_32_bits(wptr_gpu_addr)); in sdma_v4_0_gfx_resume()
1145 upper_32_bits(wptr_gpu_addr)); in sdma_v4_0_gfx_resume()
1180 u64 wptr_gpu_addr; in sdma_v4_0_page_resume() local
1227 wptr_gpu_addr = ring->wptr_gpu_addr; in sdma_v4_0_page_resume()
1229 lower_32_bits(wptr_gpu_addr)); in sdma_v4_0_page_resume()
1231 upper_32_bits(wptr_gpu_addr)); in sdma_v4_0_page_resume()
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| A D | amdgpu_ring.c | 313 ring->wptr_gpu_addr = in amdgpu_ring_init()
717 prop->wptr_gpu_addr = ring->wptr_gpu_addr; in amdgpu_ring_to_mqd_prop()
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| A D | sdma_v3_0.c | 644 u64 wptr_gpu_addr; in sdma_v3_0_gfx_resume() local
707 wptr_gpu_addr = ring->wptr_gpu_addr; in sdma_v3_0_gfx_resume()
710 lower_32_bits(wptr_gpu_addr)); in sdma_v3_0_gfx_resume()
712 upper_32_bits(wptr_gpu_addr)); in sdma_v3_0_gfx_resume()
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| A D | sdma_v4_4_2.c | 693 u64 wptr_gpu_addr; in sdma_v4_4_2_gfx_resume() local
758 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_4_2_gfx_resume()
760 lower_32_bits(wptr_gpu_addr)); in sdma_v4_4_2_gfx_resume()
762 upper_32_bits(wptr_gpu_addr)); in sdma_v4_4_2_gfx_resume()
799 u64 wptr_gpu_addr; in sdma_v4_4_2_page_resume() local
865 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_4_2_page_resume()
867 lower_32_bits(wptr_gpu_addr)); in sdma_v4_4_2_page_resume()
869 upper_32_bits(wptr_gpu_addr)); in sdma_v4_4_2_page_resume()
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| A D | sdma_v6_0.c | 490 u64 wptr_gpu_addr; in sdma_v6_0_gfx_resume_instance() local
521 wptr_gpu_addr = ring->wptr_gpu_addr; in sdma_v6_0_gfx_resume_instance()
523 lower_32_bits(wptr_gpu_addr)); in sdma_v6_0_gfx_resume_instance()
525 upper_32_bits(wptr_gpu_addr)); in sdma_v6_0_gfx_resume_instance()
871 wb_gpu_addr = prop->wptr_gpu_addr; in sdma_v6_0_mqd_init()
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| A D | sdma_v7_0.c | 483 u64 wptr_gpu_addr; in sdma_v7_0_gfx_resume_instance() local
513 wptr_gpu_addr = ring->wptr_gpu_addr; in sdma_v7_0_gfx_resume_instance()
515 lower_32_bits(wptr_gpu_addr)); in sdma_v7_0_gfx_resume_instance()
517 upper_32_bits(wptr_gpu_addr)); in sdma_v7_0_gfx_resume_instance()
891 wb_gpu_addr = prop->wptr_gpu_addr; in sdma_v7_0_mqd_init()
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| A D | sdma_v5_2.c | 546 u64 wptr_gpu_addr; in sdma_v5_2_gfx_resume_instance() local
578 wptr_gpu_addr = ring->wptr_gpu_addr; in sdma_v5_2_gfx_resume_instance()
580 lower_32_bits(wptr_gpu_addr)); in sdma_v5_2_gfx_resume_instance()
582 upper_32_bits(wptr_gpu_addr)); in sdma_v5_2_gfx_resume_instance()
878 wb_gpu_addr = prop->wptr_gpu_addr; in sdma_v5_2_mqd_init()
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| A D | sdma_v5_0.c | 697 u64 wptr_gpu_addr; in sdma_v5_0_gfx_resume_instance() local
728 wptr_gpu_addr = ring->wptr_gpu_addr; in sdma_v5_0_gfx_resume_instance()
730 lower_32_bits(wptr_gpu_addr)); in sdma_v5_0_gfx_resume_instance()
732 upper_32_bits(wptr_gpu_addr)); in sdma_v5_0_gfx_resume_instance()
978 wb_gpu_addr = prop->wptr_gpu_addr; in sdma_v5_0_mqd_init()
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| A D | amdgpu_mes.c | 301 queue_input.wptr_addr = ring->wptr_gpu_addr; in amdgpu_mes_map_legacy_queue()
353 queue_input.wptr_addr = ring->wptr_gpu_addr; in amdgpu_mes_reset_legacy_queue()
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| A D | gfx_v11_0.c | 371 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx11_kiq_map_queues()
3702 u64 rb_addr, rptr_addr, wptr_gpu_addr; in gfx_v11_0_cp_gfx_resume() local
3732 wptr_gpu_addr = ring->wptr_gpu_addr; in gfx_v11_0_cp_gfx_resume()
3734 lower_32_bits(wptr_gpu_addr)); in gfx_v11_0_cp_gfx_resume()
3736 upper_32_bits(wptr_gpu_addr)); in gfx_v11_0_cp_gfx_resume()
3769 wptr_gpu_addr = ring->wptr_gpu_addr; in gfx_v11_0_cp_gfx_resume()
3771 lower_32_bits(wptr_gpu_addr)); in gfx_v11_0_cp_gfx_resume()
3773 upper_32_bits(wptr_gpu_addr)); in gfx_v11_0_cp_gfx_resume()
4118 wb_gpu_addr = prop->wptr_gpu_addr; in gfx_v11_0_gfx_mqd_init()
4297 wb_gpu_addr = prop->wptr_gpu_addr; in gfx_v11_0_compute_mqd_init()
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| A D | gfx_v12_0.c | 311 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx_v12_0_kiq_map_queues()
2715 u64 rb_addr, rptr_addr, wptr_gpu_addr; in gfx_v12_0_cp_gfx_resume() local
2745 wptr_gpu_addr = ring->wptr_gpu_addr; in gfx_v12_0_cp_gfx_resume()
2747 lower_32_bits(wptr_gpu_addr)); in gfx_v12_0_cp_gfx_resume()
2749 upper_32_bits(wptr_gpu_addr)); in gfx_v12_0_cp_gfx_resume()
3015 wb_gpu_addr = prop->wptr_gpu_addr; in gfx_v12_0_gfx_mqd_init()
3191 wb_gpu_addr = prop->wptr_gpu_addr; in gfx_v12_0_compute_mqd_init()
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| A D | amdgpu_ring.h | 373 u64 wptr_gpu_addr; member
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| A D | gfx_v10_0.c | 3730 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx10_kiq_map_queues()
6504 u64 rb_addr, rptr_addr, wptr_gpu_addr; in gfx_v10_0_cp_gfx_resume() local
6537 wptr_gpu_addr = ring->wptr_gpu_addr; in gfx_v10_0_cp_gfx_resume()
6539 lower_32_bits(wptr_gpu_addr)); in gfx_v10_0_cp_gfx_resume()
6541 upper_32_bits(wptr_gpu_addr)); in gfx_v10_0_cp_gfx_resume()
6574 wptr_gpu_addr = ring->wptr_gpu_addr; in gfx_v10_0_cp_gfx_resume()
6576 lower_32_bits(wptr_gpu_addr)); in gfx_v10_0_cp_gfx_resume()
6578 upper_32_bits(wptr_gpu_addr)); in gfx_v10_0_cp_gfx_resume()
6810 wb_gpu_addr = prop->wptr_gpu_addr; in gfx_v10_0_gfx_mqd_init()
6994 wb_gpu_addr = prop->wptr_gpu_addr; in gfx_v10_0_compute_mqd_init()
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| A D | amdgpu_userq_fence.c | 367 addr = queue->userq_prop->wptr_gpu_addr; in amdgpu_userq_fence_read_wptr()
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| A D | gfx_v8_0.c | 4228 u64 rb_addr, rptr_addr, wptr_gpu_addr; in gfx_v8_0_cp_gfx_resume() local
4258 wptr_gpu_addr = ring->wptr_gpu_addr; in gfx_v8_0_cp_gfx_resume()
4259 WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); in gfx_v8_0_cp_gfx_resume()
4260 WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); in gfx_v8_0_cp_gfx_resume()
4338 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx_v8_0_kiq_kcq_enable()
4468 wb_gpu_addr = ring->wptr_gpu_addr; in gfx_v8_0_mqd_init()
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| A D | gfx_v9_0.c | 955 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx_v9_0_kiq_map_queues()
3391 u64 rb_addr, rptr_addr, wptr_gpu_addr; in gfx_v9_0_cp_gfx_resume() local
3419 wptr_gpu_addr = ring->wptr_gpu_addr; in gfx_v9_0_cp_gfx_resume()
3420 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); in gfx_v9_0_cp_gfx_resume()
3421 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); in gfx_v9_0_cp_gfx_resume()
3642 wb_gpu_addr = ring->wptr_gpu_addr; in gfx_v9_0_mqd_init()
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| A D | amdgpu.h | 872 uint64_t wptr_gpu_addr; member
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| A D | mes_v11_0.c | 1126 wb_gpu_addr = ring->wptr_gpu_addr; in mes_v11_0_mqd_init()
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| A D | mes_v12_0.c | 1208 wb_gpu_addr = ring->wptr_gpu_addr; in mes_v12_0_mqd_init()
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| A D | gfx_v7_0.c | 2884 wb_gpu_addr = ring->wptr_gpu_addr; in gfx_v7_0_mqd_init()
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| /drivers/gpu/drm/amd/amdkfd/ |
| A D | kfd_kernel_queue.h | 71 uint64_t wptr_gpu_addr; member
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| A D | kfd_kernel_queue.c | 124 kq->wptr_gpu_addr = kq->wptr_mem->gpu_addr; in kq_initialize()
139 prop.write_ptr = (uint32_t *) kq->wptr_gpu_addr; in kq_initialize()
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