Searched refs:wptr_offset (Results 1 – 11 of 11) sorted by relevance
| /drivers/gpu/drm/amd/display/dmub/ |
| A D | dmub_srv.h | 433 void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
453 void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
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| /drivers/gpu/drm/amd/display/dmub/src/ |
| A D | dmub_dcn20.c | 296 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) in dmub_dcn20_set_inbox1_wptr() argument
298 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn20_set_inbox1_wptr()
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| A D | dmub_dcn31.c | 261 void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) in dmub_dcn31_set_inbox1_wptr() argument
263 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn31_set_inbox1_wptr()
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| A D | dmub_dcn35.c | 297 void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) in dmub_dcn35_set_inbox1_wptr() argument
299 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn35_set_inbox1_wptr()
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| A D | dmub_dcn32.c | 285 void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) in dmub_dcn32_set_inbox1_wptr() argument
287 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn32_set_inbox1_wptr()
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| A D | dmub_dcn20.h | 210 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
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| A D | dmub_dcn401.c | 277 void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) in dmub_dcn401_set_inbox1_wptr() argument
279 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn401_set_inbox1_wptr()
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| A D | dmub_dcn31.h | 212 void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
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| A D | dmub_dcn32.h | 219 void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
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| A D | dmub_dcn35.h | 232 void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
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| A D | dmub_dcn401.h | 229 void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
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