| /drivers/gpu/drm/xe/ |
| A D | xe_huc.c | 138 u32 wr_offset, u32 huc_offset, u32 huc_size) in huc_emit_pxp_auth_msg() argument
142 huc_auth_msg_wr(xe, map, wr_offset, header.api_version, PXP_APIVER(4, 3)); in huc_emit_pxp_auth_msg()
144 huc_auth_msg_wr(xe, map, wr_offset, header.status, 0); in huc_emit_pxp_auth_msg()
145 huc_auth_msg_wr(xe, map, wr_offset, header.buffer_len, in huc_emit_pxp_auth_msg()
147 huc_auth_msg_wr(xe, map, wr_offset, huc_base_address, huc_offset); in huc_emit_pxp_auth_msg()
148 huc_auth_msg_wr(xe, map, wr_offset, huc_size, huc_size); in huc_emit_pxp_auth_msg()
150 return wr_offset + sizeof(struct pxp43_new_huc_auth_in); in huc_emit_pxp_auth_msg()
158 u32 wr_offset; in huc_auth_via_gsccs() local
170 wr_offset = xe_gsc_emit_header(xe, &pkt->vmap, 0, HECI_MEADDRESS_PXP, 0, in huc_auth_via_gsccs()
172 wr_offset = huc_emit_pxp_auth_msg(xe, &pkt->vmap, wr_offset, in huc_auth_via_gsccs()
[all …]
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| A D | xe_gsc.c | 115 static u32 emit_version_query_msg(struct xe_device *xe, struct iosys_map *map, u32 wr_offset) in emit_version_query_msg() argument
117 xe_map_memset(xe, map, wr_offset, 0, sizeof(struct gsc_get_compatibility_version_in)); in emit_version_query_msg()
119 version_query_wr(xe, map, wr_offset, header.group_id, MKHI_GROUP_ID_GFX_SRV); in emit_version_query_msg()
120 version_query_wr(xe, map, wr_offset, header.command, in emit_version_query_msg()
123 return wr_offset + sizeof(struct gsc_get_compatibility_version_in); in emit_version_query_msg()
134 u32 wr_offset; in query_compatibility_version() local
150 wr_offset = xe_gsc_emit_header(xe, &bo->vmap, 0, HECI_MEADDRESS_MKHI, 0, in query_compatibility_version()
152 wr_offset = emit_version_query_msg(xe, &bo->vmap, wr_offset); in query_compatibility_version()
154 err = xe_gsc_pkt_submit_kernel(gsc, ggtt_offset, wr_offset, in query_compatibility_version()
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| A D | xe_gsc_proxy.c | 227 u32 wr_offset; in proxy_query() local
232 wr_offset = xe_gsc_emit_header(xe, &gsc->proxy.to_gsc, 0, in proxy_query()
234 wr_offset = emit_proxy_header(xe, &gsc->proxy.to_gsc, wr_offset); in proxy_query()
236 size = wr_offset; in proxy_query()
312 wr_offset = xe_gsc_emit_header(xe, &gsc->proxy.to_gsc, 0, in proxy_query()
316 xe_map_memcpy_to(xe, &gsc->proxy.to_gsc, wr_offset, gsc->proxy.from_csme, size); in proxy_query()
318 size += wr_offset; in proxy_query()
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| A D | xe_pxp_submit.c | 405 u32 wr_offset; in gsccs_send_message() local
415 wr_offset = xe_gsc_emit_header(xe, &gsc_res->msg_in, 0, in gsccs_send_message()
422 xe_map_memcpy_to(xe, &gsc_res->msg_in, wr_offset, in gsccs_send_message()
435 wr_offset + msg_in_size, PXP_BB_SIZE + gsc_res->inout_size, in gsccs_send_message()
436 wr_offset + msg_out_size_max); in gsccs_send_message()
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| /drivers/bus/mhi/ep/ |
| A D | ring.c | 42 if (ring->wr_offset == end) in __mhi_ep_cache_ring()
45 start = ring->wr_offset; in __mhi_ep_cache_ring()
81 size_t wr_offset; in mhi_ep_cache_ring() local
84 wr_offset = mhi_ep_ring_addr2offset(ring, wr_ptr); in mhi_ep_cache_ring()
87 ret = __mhi_ep_cache_ring(ring, wr_offset); in mhi_ep_cache_ring()
91 ring->wr_offset = wr_offset; in mhi_ep_cache_ring()
122 if (ring->rd_offset < ring->wr_offset) in mhi_ep_ring_add_element()
123 num_free_elem = (ring->wr_offset - ring->rd_offset) - 1; in mhi_ep_ring_add_element()
125 num_free_elem = ((ring->ring_size - ring->rd_offset) + ring->wr_offset) - 1; in mhi_ep_ring_add_element()
205 ring->wr_offset = mhi_ep_ring_addr2offset(ring, le64_to_cpu(val)); in mhi_ep_ring_start()
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| A D | internal.h | 132 size_t wr_offset; member
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| A D | main.c | 333 return !!(mhi_chan->rd_offset == ring->wr_offset); in mhi_ep_queue_is_empty()
796 if (ring->rd_offset == ring->wr_offset) in mhi_ep_cmd_ring_worker()
803 while (ring->rd_offset != ring->wr_offset) { in mhi_ep_cmd_ring_worker()
857 if (chan->rd_offset == ring->wr_offset) { in mhi_ep_ch_ring_worker()
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| /drivers/gpu/drm/imagination/ |
| A D | pvr_ccb.c | 218 u32 wr_offset = READ_ONCE(ctrl->write_offset); in pvr_kccb_used_slot_count_locked() local
224 if (wr_offset >= rd_offset) in pvr_kccb_used_slot_count_locked()
225 used_count = wr_offset - rd_offset; in pvr_kccb_used_slot_count_locked()
227 used_count = wr_offset + pvr_dev->kccb.slot_count - rd_offset; in pvr_kccb_used_slot_count_locked()
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| /drivers/spi/ |
| A D | spi-mtk-snfi.c | 1060 u32 wr_offset = 0; in mtk_snand_write_page_cache() local
1080 wr_offset = op_addr & mask; in mtk_snand_write_page_cache()
1086 if (wr_offset) in mtk_snand_write_page_cache()
1087 memset(snf->buf, 0xff, wr_offset); in mtk_snand_write_page_cache()
1089 cap_len = snf->buf_len - wr_offset; in mtk_snand_write_page_cache()
1092 memcpy(snf->buf + wr_offset, op->data.buf.out, cap_len); in mtk_snand_write_page_cache()
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