Home
last modified time | relevance | path

Searched refs:writeq (Results 1 – 25 of 197) sorted by relevance

12345678

/drivers/net/ethernet/mellanox/mlxbf_gige/
A Dmlxbf_gige_rx.c43 writeq(control, base + MLXBF_GIGE_CONTROL); in mlxbf_gige_enable_mac_rx_filter()
55 writeq(control, base + MLXBF_GIGE_CONTROL); in mlxbf_gige_disable_mac_rx_filter()
64 writeq(dmac, base + MLXBF_GIGE_RX_MAC_FILTER + in mlxbf_gige_set_mac_rx_filter()
87 writeq(control, base + MLXBF_GIGE_CONTROL); in mlxbf_gige_enable_promisc()
105 writeq(control, base + MLXBF_GIGE_CONTROL); in mlxbf_gige_disable_promisc()
175 writeq(data, priv->base + MLXBF_GIGE_RX); in mlxbf_gige_rx_init()
178 writeq(MLXBF_GIGE_RX_MAC_FILTER_COUNT_DISC_EN, in mlxbf_gige_rx_init()
180 writeq(MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS_EN, in mlxbf_gige_rx_init()
183 writeq(ilog2(priv->rx_q_entries), in mlxbf_gige_rx_init()
196 writeq(data, priv->base + MLXBF_GIGE_RX_DMA); in mlxbf_gige_rx_init()
[all …]
A Dmlxbf_gige_tx.c31 writeq(priv->tx_wqe_base_dma, priv->base + MLXBF_GIGE_TX_WQ_BASE); in mlxbf_gige_tx_init()
43 writeq(priv->tx_cc_dma, priv->base + MLXBF_GIGE_TX_CI_UPDATE_ADDRESS); in mlxbf_gige_tx_init()
45 writeq(ilog2(priv->tx_q_entries), in mlxbf_gige_tx_init()
88 writeq(0, priv->base + MLXBF_GIGE_TX_WQ_BASE); in mlxbf_gige_tx_deinit()
89 writeq(0, priv->base + MLXBF_GIGE_TX_CI_UPDATE_ADDRESS); in mlxbf_gige_tx_deinit()
267 writeq(priv->tx_pi, priv->base + MLXBF_GIGE_TX_PRODUCER_INDEX); in mlxbf_gige_start_xmit()
/drivers/net/ethernet/marvell/octeontx2/af/
A Dptp.c259 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP); in ptp_atomic_update()
260 writeq(timestamp / NSEC_PER_SEC, in ptp_atomic_update()
272 writeq(regval, ptp->reg_base + PTP_CLOCK_CFG); in ptp_atomic_update()
302 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP); in ptp_atomic_adjtime()
308 writeq(regval, ptp->reg_base + PTP_CLOCK_CFG); in ptp_atomic_adjtime()
354 writeq(comp, ptp->reg_base + PTP_CLOCK_COMP); in ptp_adjfine()
389 writeq(0, ptp->reg_base + PTP_NANO_TIMESTAMP); in ptp_start()
390 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP); in ptp_start()
391 writeq(0, ptp->reg_base + PTP_SEC_TIMESTAMP); in ptp_start()
486 writeq(0, ptp->reg_base + PTP_PPS_THRESH_HI); in ptp_pps_on()
[all …]
/drivers/infiniband/hw/hfi1/
A Dpio_copy.c38 writeq(pbc, dest); in pio_copy()
51 writeq(*(u64 *)from, dest); in pio_copy()
67 writeq(*(u64 *)from, dest); in pio_copy()
86 writeq(*(u64 *)from, dest); in pio_copy()
97 writeq(*(u64 *)from, dest); in pio_copy()
110 writeq(val.val64, dest); in pio_copy()
118 writeq(0, dest); in pio_copy()
224 writeq(temp, dest); in merge_write8()
233 writeq(carry.val64, dest); in carry8_write8()
269 writeq(pbc, dest); in seg_pio_copy_start()
[all …]
/drivers/cache/
A Dstarfive_starlink_cache.c49 writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr), in starlink_cache_dma_cache_wback()
51 writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size), in starlink_cache_dma_cache_wback()
55 writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK, in starlink_cache_dma_cache_wback()
64 writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr), in starlink_cache_dma_cache_invalidate()
66 writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size), in starlink_cache_dma_cache_invalidate()
70 writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK, in starlink_cache_dma_cache_invalidate()
79 writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr), in starlink_cache_dma_cache_wback_inv()
81 writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size), in starlink_cache_dma_cache_wback_inv()
85 writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK, in starlink_cache_dma_cache_wback_inv()
/drivers/net/ethernet/neterion/
A Ds2io.c1213 writeq(val64, &bar0->sw_reset); in init_nic()
1220 writeq(val64, &bar0->sw_reset); in init_nic()
1338 writeq(val64, &bar0->tx_pa_cfg); in init_nic()
1746 writeq(val64, &bar0->mac_cfg); in init_nic()
1848 writeq(temp64, addr); in do_s2io_write_bits()
2242 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2248 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
3420 writeq(val64, &bar0->sw_reset); in s2io_reset()
3780 writeq(rx_mat, &bar0->rx_mat); in s2io_enable_msi_x()
4345 writeq(val64, addr); in do_s2io_chk_alarm_bit()
[all …]
/drivers/fpga/
A Ddfl-fme-error.c73 writeq(GENMASK_ULL(63, 0), base + PCIE0_ERROR_MASK); in pcie0_errors_store()
77 writeq(v, base + PCIE0_ERROR); in pcie0_errors_store()
81 writeq(0ULL, base + PCIE0_ERROR_MASK); in pcie0_errors_store()
118 writeq(GENMASK_ULL(63, 0), base + PCIE1_ERROR_MASK); in pcie1_errors_store()
122 writeq(v, base + PCIE1_ERROR); in pcie1_errors_store()
126 writeq(0ULL, base + PCIE1_ERROR_MASK); in pcie1_errors_store()
196 writeq(v, base + RAS_ERROR_INJECT); in inject_errors_store()
234 writeq(GENMASK_ULL(63, 0), base + FME_ERROR_MASK); in fme_errors_store()
238 writeq(v, base + FME_ERROR); in fme_errors_store()
243 writeq(dfl_feature_revision(base) ? 0ULL : MBP_ERROR, in fme_errors_store()
[all …]
A Ddfl-fme-mgr.c102 writeq(pr_error, fme_pr + FME_PR_ERR); in fme_mgr_pr_error_handle()
125 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_init()
136 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_init()
160 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_init()
178 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write()
211 writeq(pr_data, fme_pr + FME_PR_DATA); in fme_mgr_write()
230 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_complete()
/drivers/mmc/host/
A Dcavium.c212 writeq(emm_switch, host->base + MIO_EMM_SWITCH(host)); in do_switch()
215 writeq(emm_switch, host->base + MIO_EMM_SWITCH(host)); in do_switch()
267 writeq(wdog, slot->host->base + MIO_EMM_WDOG(host)); in cvm_mmc_reset_bus()
293 writeq(emm_sample, host->base + MIO_EMM_SAMPLE(host)); in cvm_mmc_switch_to()
432 writeq(emm_dma, host->base + MIO_EMM_DMA(host)); in cleanup_dma()
449 writeq(emm_int, host->base + MIO_EMM_INT(host)); in cvm_mmc_interrupt()
697 writeq(emm_dma, host->base + MIO_EMM_DMA(host)); in cvm_mmc_dma_request()
742 writeq(dat, host->base + MIO_EMM_BUF_DAT(host)); in do_write_request()
805 writeq(0, host->base + MIO_EMM_STS_MASK(host)); in cvm_mmc_request()
819 writeq(emm_cmd, host->base + MIO_EMM_CMD(host)); in cvm_mmc_request()
[all …]
A Dcavium-thunderx.c33 writeq(val, host->base + MIO_EMM_INT(host)); in thunder_mmc_int_enable()
34 writeq(val, host->base + MIO_EMM_INT_EN_SET(host)); in thunder_mmc_int_enable()
123 writeq(127, host->base + MIO_EMM_INT_EN(host)); in thunder_mmc_probe()
124 writeq(3, host->base + MIO_EMM_DMA_INT_ENA_W1C(host)); in thunder_mmc_probe()
126 writeq(BIT_ULL(16), host->base + MIO_EMM_DMA_FIFO_CFG(host)); in thunder_mmc_probe()
182 writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host)); in thunder_mmc_remove()
A Dcavium-octeon.c96 writeq(0, (void __iomem *)CVMX_MIO_BOOT_CTL); in octeon_mmc_acquire_bus()
112 writeq(val, host->base + MIO_EMM_INT(host)); in octeon_mmc_int_enable()
114 writeq(val, host->base + MIO_EMM_INT_EN(host)); in octeon_mmc_int_enable()
235 writeq(val, host->base + MIO_EMM_INT(host)); in octeon_mmc_probe()
311 writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host)); in octeon_mmc_remove()
/drivers/gpio/
A Dgpio-mlxbf.c114 writeq(gs->csave_regs.scratchpad, gs->base + MLXBF_GPIO_SCRATCHPAD); in mlxbf_gpio_resume()
115 writeq(gs->csave_regs.pad_control[0], in mlxbf_gpio_resume()
117 writeq(gs->csave_regs.pad_control[1], in mlxbf_gpio_resume()
119 writeq(gs->csave_regs.pad_control[2], in mlxbf_gpio_resume()
121 writeq(gs->csave_regs.pad_control[3], in mlxbf_gpio_resume()
123 writeq(gs->csave_regs.pin_dir_i, gs->base + MLXBF_GPIO_PIN_DIR_I); in mlxbf_gpio_resume()
124 writeq(gs->csave_regs.pin_dir_o, gs->base + MLXBF_GPIO_PIN_DIR_O); in mlxbf_gpio_resume()
A Dgpio-thunderx.c113 writeq(txgpio->line_entries[line].fil_bits, in thunderx_gpio_dir_in()
129 writeq(BIT_ULL(bank_bit), reg); in thunderx_gpio_set()
153 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_dir_out()
241 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_set_config()
285 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); in thunderx_gpio_set_multiple()
286 writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR); in thunderx_gpio_set_multiple()
297 writeq(GPIO_INTR_INTR, in thunderx_gpio_irq_ack()
306 writeq(GPIO_INTR_ENA_W1C, in thunderx_gpio_irq_mask()
315 writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR, in thunderx_gpio_irq_mask_ack()
324 writeq(GPIO_INTR_ENA_W1S, in thunderx_gpio_irq_unmask()
[all …]
/drivers/mailbox/
A Dqcom-cpucp-mbox.c65 writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR); in qcom_cpucp_mbox_irq_fn()
80 writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); in qcom_cpucp_mbox_startup()
93 writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); in qcom_cpucp_mbox_shutdown()
132 writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); in qcom_cpucp_mbox_probe()
133 writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR); in qcom_cpucp_mbox_probe()
134 writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP); in qcom_cpucp_mbox_probe()
145 writeq(APSS_CPUCP_RX_MBOX_CMD_MASK, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP); in qcom_cpucp_mbox_probe()
/drivers/watchdog/
A Dmarvell_gti_wdt.c90 writeq(GTI_CWD_INT_PENDING_STATUS(priv->wdt_timer_idx), in gti_wdt_interrupt()
102 writeq(GTI_CWD_POKE_VAL, in gti_wdt_ping()
119 writeq(GTI_CWD_INT_PENDING_STATUS(priv->wdt_timer_idx), in gti_wdt_start()
123 writeq(GTI_CWD_INT_ENA_SET_VAL(priv->wdt_timer_idx), in gti_wdt_start()
129 writeq(regval, priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx)); in gti_wdt_start()
140 writeq(GTI_CWD_INT_ENA_CLR_VAL(priv->wdt_timer_idx), in gti_wdt_stop()
146 writeq(regval, priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx)); in gti_wdt_stop()
182 writeq(regval, priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx)); in gti_wdt_settimeout()
195 writeq(GTI_CWD_INT_ENA_CLR_VAL(priv->wdt_timer_idx), in gti_wdt_set_pretimeout()
/drivers/net/ethernet/cavium/liquidio/
A Docteon_mailbox.c80 writeq(OCTEON_PFVFERR, in octeon_mbox_read()
115 writeq(OCTEON_PFVFACK, mbox->mbox_read_reg); in octeon_mbox_read()
172 writeq(mbox_cmd->msg.u64, mbox->mbox_write_reg); in octeon_mbox_write()
184 writeq(mbox_cmd->data[i], mbox->mbox_write_reg); in octeon_mbox_write()
193 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_write()
306 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
316 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
325 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
341 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
371 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_cancel()
A Dcn23xx_pf_device.c297 writeq((readq(inst_cnt_reg) & in cn23xx_pf_setup_global_input_regs()
382 writeq(readq((u8 *)oct->mmio[0].hw_addr + in cn23xx_pf_setup_global_output_regs()
388 writeq(0xffffffffffffffffULL, in cn23xx_pf_setup_global_output_regs()
391 writeq(0xffffffffffffffffULL, in cn23xx_pf_setup_global_output_regs()
453 writeq(pkt_in_done, iq->inst_cnt_reg); in cn23xx_setup_iq_regs()
520 writeq(mbox_int_val, mbox->mbox_int_reg); in cn23xx_pf_mbox_thread()
825 writeq(BIT_ULL(q_no), in cn23xx_handle_pf_mbox_intr()
866 writeq(intr64, cn23xx->intr_sum_reg64); in cn23xx_interrupt_handler()
944 writeq(intr_val, cn23xx->intr_enb_reg64); in cn23xx_enable_pf_interrupt()
962 writeq(0, cn23xx->intr_enb_reg64); in cn23xx_disable_pf_interrupt()
[all …]
/drivers/crypto/marvell/octeontx/
A Dotx_cptpf_mbox.c78 writeq(mbx->data, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 1)); in otx_cpt_send_msg_to_vf()
79 writeq(mbx->msg, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 0)); in otx_cpt_send_msg_to_vf()
106 writeq(1ull << vf, cpt->reg_base + OTX_CPT_PF_MBOX_INTX(0)); in otx_cpt_clear_mbox_intr()
120 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(vf)); in otx_cpt_cfg_qlen_for_vf()
132 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(vf)); in otx_cpt_cfg_vq_priority()
162 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(q)); in otx_cpt_bind_vq_to_grp()
A Dotx_cptvf_main.c351 writeq(vqx_ctl.u, cptvf->reg_base + OTX_CPT_VQX_CTL(0)); in cptvf_write_vq_ctl()
360 writeq(vqx_dbell.u, cptvf->reg_base + OTX_CPT_VQX_DOORBELL(0)); in otx_cptvf_write_vq_doorbell()
369 writeq(vqx_inprg.u, cptvf->reg_base + OTX_CPT_VQX_INPROG(0)); in cptvf_write_vq_inprog()
378 writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); in cptvf_write_vq_done_numwait()
395 writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); in cptvf_write_vq_done_timewait()
444 writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); in cptvf_clear_dovf_intr()
454 writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); in cptvf_clear_irde_intr()
464 writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); in cptvf_clear_nwrp_intr()
474 writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); in cptvf_clear_mbox_intr()
484 writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); in cptvf_clear_swerr_intr()
[all …]
/drivers/edac/
A Dthunderx_edac.c275 writeq(val, pdata->regs + _reg); \
309 writeq(val, lmc->regs + LMC_INT_W1S); in thunderx_lmc_inject_int_write()
547 writeq(0, lmc->regs + LMC_CHAR_MASK0); in thunderx_lmc_err_isr()
548 writeq(0, lmc->regs + LMC_CHAR_MASK2); in thunderx_lmc_err_isr()
562 writeq(ctx->reg_int, lmc->regs + LMC_INT); in thunderx_lmc_err_isr()
772 writeq(lmc_int, lmc->regs + LMC_INT); in thunderx_lmc_probe()
1438 writeq(OCX_LNE_INT_ENA_ALL, in thunderx_ocx_probe()
1442 writeq(reg, ocx->regs + OCX_LNE_INT(i)); in thunderx_ocx_probe()
1450 writeq(OCX_COM_LINKX_INT_ENA_ALL, in thunderx_ocx_probe()
1455 writeq(reg, ocx->regs + OCX_COM_INT); in thunderx_ocx_probe()
[all …]
/drivers/spi/
A Dspi-cavium.c66 writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG(p)); in octeon_spi_do_transfer()
78 writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i)); in octeon_spi_do_transfer()
85 writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p)); in octeon_spi_do_transfer()
102 writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i)); in octeon_spi_do_transfer()
113 writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p)); in octeon_spi_do_transfer()
/drivers/char/hw_random/
A Dcavium-rng.c42 writeq(THUNDERX_RNM_RNG_EN | THUNDERX_RNM_ENT_EN, in cavium_rng_probe()
51 writeq(0, rng->control_status); in cavium_rng_probe()
72 writeq(0, rng->control_status); in cavium_rng_remove()
/drivers/net/ethernet/cavium/common/
A Dcavium_ptp.c129 writeq(comp, clock->reg_base + PTP_CLOCK_COMP); in cavium_ptp_adjfine()
276 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
279 writeq(clock_comp, clock->reg_base + PTP_CLOCK_COMP); in cavium_ptp_probe()
293 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
322 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_remove()
/drivers/perf/
A Dstarfive_starlink_pmu.c169 writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_CYCLE_COUNTER); in starlink_pmu_set_event_period()
171 writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_EVENT_COUNTER + in starlink_pmu_set_event_period()
200 writeq(event->hw.config, starlink_pmu->pmu_base + in starlink_pmu_counter_start()
206 writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_INTERRUPT_ENABLE); in starlink_pmu_counter_start()
208 writeq(STARLINK_PMU_GLOBAL_ENABLE, starlink_pmu->pmu_base + in starlink_pmu_counter_start()
221 writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_CONTROL); in starlink_pmu_counter_stop()
229 writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_INTERRUPT_ENABLE); in starlink_pmu_counter_stop()
417 writeq(BIT_ULL(idx), starlink_pmu->pmu_base + in starlink_pmu_handle_irq()
/drivers/misc/ocxl/
A Dmmio.c100 writeq(val, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_write64()
163 writeq(tmp, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_set64()
226 writeq(tmp, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_clear64()
230 writeq(tmp, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_clear64()

Completed in 65 milliseconds

12345678