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Searched refs:xe_mmio_wait32 (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/xe/compat-i915-headers/
A Dintel_uncore.h100 return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value, in intel_wait_for_register()
111 return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value, in intel_wait_for_register_fw()
131 return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value, in __intel_wait_for_register()
/drivers/gpu/drm/xe/
A Dxe_device.c547 ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false); in __xe_driver_flr()
558 ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false); in __xe_driver_flr()
565 ret = xe_mmio_wait32(mmio, GU_DEBUG, DRIVERFLR_STATUS, DRIVERFLR_STATUS, in __xe_driver_flr()
1007 if (xe_mmio_wait32(&gt->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0, in tdf_request_sync()
1032 if (xe_mmio_wait32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 500, NULL, true)) in xe_device_l2_flush()
A Dxe_mmio.h28 int xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,
A Dxe_force_wake.c112 ret = xe_mmio_wait32(&gt->mmio, domain->reg_ack, domain->val, wake ? domain->val : 0, in __domain_wait()
A Dxe_pcode.c75 err = xe_mmio_wait32(mmio, PCODE_MAILBOX, PCODE_READY, 0, in __pcode_mailbox_rw()
A Dxe_huc.c271 ret = xe_mmio_wait32(&gt->mmio, huc_auth_modes[type].reg, huc_auth_modes[type].val, in xe_huc_auth()
A Dxe_guc.c902 ret = xe_mmio_wait32(mmio, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false); in xe_guc_reset()
1425 ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, in xe_guc_mmio_send_recv()
1457 ret = xe_mmio_wait32(mmio, reply_reg, resp_mask, resp_mask, in xe_guc_mmio_send_recv()
A Dxe_mmio.c391 int xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us, in xe_mmio_wait32() function
A Dxe_gsc_proxy.c80 return xe_mmio_wait32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE), in xe_gsc_wait_for_proxy_init_done()
A Dxe_gt_mcr.c625 ret = xe_mmio_wait32(&gt->mmio, STEER_SEMAPHORE, 0x1, 0x1, 10, NULL, in mcr_lock()
A Dxe_gsc.c196 return xe_mmio_wait32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE), in gsc_fw_wait()
A Dxe_pxp.c129 return xe_mmio_wait32(&gt->mmio, KCR_SIP, mask, in_play ? mask : 0, in pxp_wait_for_session_state()
A Dxe_gt.c721 err = xe_mmio_wait32(&gt->mmio, GDRST, GRDOM_FULL, 0, 5000, NULL, false); in do_gt_reset()
A Dxe_uc_fw.c880 ret = xe_mmio_wait32(mmio, DMA_CTRL, START_DMA, 0, 100000, &dma_ctrl, in uc_fw_xfer()
A Dxe_oa.c495 if (xe_mmio_wait32(mmio, __oa_regs(stream)->oa_ctrl, in xe_oa_disable()
503 if (xe_mmio_wait32(mmio, OA_TLB_INV_CR, 1, 0, 50000, NULL, false)) in xe_oa_disable()

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