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Searched refs:GENMASK (Results 1 – 25 of 144) sorted by relevance

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/include/soc/mscc/
A Docelot_ana.h16 #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
25 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
29 #define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)
33 #define ANA_AUTOAGE_AGE_PERIOD_M GENMASK(20, 1)
41 #define ANA_AGENCTRL_FID_MASK_M GENMASK(23, 12)
62 #define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6)
65 #define ANA_FLOODING_FLD_MULTICAST_M GENMASK(5, 0)
74 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6)
77 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_M GENMASK(5, 0)
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A Docelot_qsys.h26 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
29 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)
34 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
37 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0)
42 #define QSYS_QMAP_SE_BASE_M GENMASK(12, 5)
45 #define QSYS_QMAP_SE_IDX_SEL_M GENMASK(4, 2)
48 #define QSYS_QMAP_SE_INP_SEL_M GENMASK(1, 0)
55 #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M GENMASK(18, 9)
60 #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M GENMASK(6, 0)
68 #define QSYS_RED_PROFILE_WM_RED_HIGH_M GENMASK(7, 0)
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A Docelot_hsio.h91 #define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
94 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
104 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M GENMASK(11, 6)
107 #define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M GENMASK(5, 0)
115 #define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M GENMASK(13, 6)
141 #define HSIO_PLL5G_CFG2_GAIN_TEST_M GENMASK(9, 5)
167 #define HSIO_PLL5G_CFG3_FBDIVSEL_M GENMASK(7, 0)
195 #define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M GENMASK(5, 0)
202 #define HSIO_PLL5G_STATUS0_READBACK_DATA_M GENMASK(8, 1)
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A Docelot_sys.h21 #define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0)
24 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10)
27 #define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0)
41 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6)
44 #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M GENMASK(5, 0)
47 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M GENMASK(17, 9)
50 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M GENMASK(8, 0)
75 #define SYS_MMGT_FAST_FREEVLD_M GENMASK(7, 4)
78 #define SYS_MMGT_FAST_RELVLD_M GENMASK(3, 0)
83 #define SYS_EVENTS_DIF_EV_DRX_M GENMASK(8, 6)
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A Docelot_dev.h18 #define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
28 #define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
31 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
34 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
39 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M GENMASK(11, 4)
42 #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M GENMASK(3, 0)
52 #define DEV_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16)
63 #define DEV_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8)
66 #define DEV_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4)
69 #define DEV_MAC_IFG_CFG_RX_IFG1_M GENMASK(3, 0)
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/include/linux/mfd/
A Dtps68470.h57 #define TPS68470_REG_RESET_MASK GENMASK(7, 0)
58 #define TPS68470_VAVAL_AVOLT_MASK GENMASK(6, 0)
60 #define TPS68470_VDVAL_DVOLT_MASK GENMASK(5, 0)
67 #define TPS68470_VACTL_EN_MASK GENMASK(0, 0)
68 #define TPS68470_VDCTL_EN_MASK GENMASK(0, 0)
69 #define TPS68470_VCMCTL_EN_MASK GENMASK(0, 0)
71 #define TPS68470_VAUX1CTL_EN_MASK GENMASK(0, 0)
73 #define TPS68470_PLL_EN_MASK GENMASK(0, 0)
81 #define TPS68470_PLLSWR_DEFAULT GENMASK(1, 0)
86 #define TPS68470_CLK_SRC_SHIFT GENMASK(2, 0)
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A Dtps6594.h282 #define TPS6594_MASK_LDO_PLDN GENMASK(6, 5)
330 #define TPS6594_MASK_GPIO_SEL GENMASK(7, 5)
857 #define TPS6594_MASK_HOUR_0 GENMASK(3, 0)
858 #define TPS6594_MASK_HOUR_1 GENMASK(5, 4)
862 #define TPS6594_MASK_DAY_0 GENMASK(3, 0)
863 #define TPS6594_MASK_DAY_1 GENMASK(5, 4)
870 #define TPS6594_MASK_YEAR_0 GENMASK(3, 0)
871 #define TPS6594_MASK_YEAR_1 GENMASK(7, 4)
874 #define TPS6594_MASK_WEEK GENMASK(2, 0)
900 #define TPS6594_MASK_EVERY GENMASK(1, 0)
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A Dsun4i-gpadc.h12 #define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY(x) ((GENMASK(7, 0) & (x)) << 24)
15 #define SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(x) ((GENMASK(1, 0) & (x)) << 20)
16 #define SUN4I_GPADC_CTRL0_FS_DIV(x) ((GENMASK(3, 0) & (x)) << 16)
17 #define SUN4I_GPADC_CTRL0_T_ACQ(x) (GENMASK(15, 0) & (x))
27 #define SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(2, 0) & (x))
28 #define SUN4I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(2, 0)
35 #define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x))
36 #define SUN6I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(3, 0)
47 #define SUN4I_GPADC_CTRL2_PRE_MEA_THRE_CNT(x) (GENMASK(23, 0) & (x))
52 #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
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A Dti_am335x_tscadc.h55 #define STEPCONFIG_MODE(val) FIELD_PREP(GENMASK(1, 0), (val))
58 #define STEPCONFIG_AVG(val) FIELD_PREP(GENMASK(4, 2), (val))
66 #define STEPCONFIG_RFP(val) FIELD_PREP(GENMASK(13, 12), (val))
68 #define STEPCONFIG_INM(val) FIELD_PREP(GENMASK(18, 15), (val))
70 #define STEPCONFIG_INP(val) FIELD_PREP(GENMASK(22, 19), (val))
78 #define STEPDELAY_OPEN(val) FIELD_PREP(GENMASK(17, 0), (val))
80 #define STEPCONFIG_MAX_OPENDLY GENMASK(17, 0)
83 #define STEPCONFIG_MAX_SAMPLE GENMASK(7, 0)
95 #define CHARGEDLY_OPEN(val) FIELD_PREP(GENMASK(17, 0), (val))
114 #define FIFOREAD_DATA_MASK GENMASK(11, 0)
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A Dstpmic1.h101 #define LDO_VOLTAGE_MASK GENMASK(6, 2)
102 #define BUCK_VOLTAGE_MASK GENMASK(7, 2)
113 #define BUCKS_PD_CR_REG_MASK GENMASK(7, 0)
114 #define BUCK_MASK_RANK_REGISTER_MASK GENMASK(3, 0)
117 #define LDO56_VREF_PD_CR_REG_MASK GENMASK(5, 0)
118 #define LDO_MASK_RANK_REGISTER_MASK GENMASK(5, 0)
145 #define BUCKS_ICCTO_CR_REG_MASK GENMASK(6, 0)
146 #define LDOS_ICCTO_CR_REG_MASK GENMASK(5, 0)
177 #define VINLOW_CTRL_REG_MASK GENMASK(7, 0)
196 #define PONKEY_TURNOFF_TIMER_MASK GENMASK(3, 0)
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A Dintel-m10-bmc.h29 #define M10BMC_N3000_MAC_BYTE4 GENMASK(7, 0)
30 #define M10BMC_N3000_MAC_BYTE3 GENMASK(15, 8)
31 #define M10BMC_N3000_MAC_BYTE2 GENMASK(23, 16)
32 #define M10BMC_N3000_MAC_BYTE1 GENMASK(31, 24)
34 #define M10BMC_N3000_MAC_BYTE6 GENMASK(7, 0)
35 #define M10BMC_N3000_MAC_BYTE5 GENMASK(15, 8)
36 #define M10BMC_N3000_MAC_COUNT GENMASK(23, 16)
39 #define M10BMC_N3000_VER_MAJOR_MSK GENMASK(23, 16)
56 #define DRBL_RSU_PROGRESS GENMASK(7, 4)
57 #define DRBL_HOST_STATUS GENMASK(11, 8)
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/include/linux/mfd/syscon/
A Datmel-mc.h21 #define AT91_MC_ABTSZ GENMASK(9, 8)
25 #define AT91_MC_ABTTYP GENMASK(11, 10)
47 #define AT91_MC_SMC_NWS GENMASK(6, 0)
50 #define AT91_MC_SMC_TDF GENMASK(11, 8)
54 #define AT91_MC_SMC_DBW GENMASK(14, 13)
58 #define AT91_MC_SMC_ACSS GENMASK(17, 16)
81 #define AT91_MC_SDRAMC_NC GENMASK(1, 0)
86 #define AT91_MC_SDRAMC_NR GENMASK(3, 2)
116 #define AT91_MC_BFC_BFCOM GENMASK(1, 0)
120 #define AT91_MC_BFC_BFCC GENMASK(3, 2)
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/include/linux/power/
A Dmax77705_charger.h44 #define MAX77705_WCIN_DTLS GENMASK(4, 3)
46 #define MAX77705_CHGIN_DTLS GENMASK(6, 5)
50 #define MAX77705_CHG_DTLS GENMASK(3, 0)
52 #define MAX77705_BAT_DTLS GENMASK(6, 4)
56 #define MAX77705_BYP_DTLS GENMASK(3, 0)
66 #define MAX77705_MODE_MASK GENMASK(3, 0)
96 #define MAX77705_CHG_CC GENMASK(5, 0)
100 #define MAX77705_TO_ITH_MASK GENMASK(2, 0)
102 #define MAX77705_TO_TIME_MASK GENMASK(5, 3)
114 #define MAX77705_CHG_PRM_MASK GENMASK(5, 0)
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/include/linux/amba/
A Dpl080.h70 #define PL080_LLI_ADDR_MASK GENMASK(31, 2)
75 #define PL080_CONTROL_PROT_MASK GENMASK(30, 28)
84 #define PL080_CONTROL_DWIDTH_MASK GENMASK(23, 21)
86 #define PL080_CONTROL_SWIDTH_MASK GENMASK(20, 18)
88 #define PL080_CONTROL_DB_SIZE_MASK GENMASK(17, 15)
90 #define PL080_CONTROL_SB_SIZE_MASK GENMASK(14, 12)
118 #define PL080_CONFIG_DST_SEL_MASK GENMASK(9, 6)
120 #define PL080_CONFIG_SRC_SEL_MASK GENMASK(4, 1)
135 #define FTDMAC020_CH_CSR_FIFOTH_MSK GENMASK(26, 24)
137 #define FTDMAC020_CH_CSR_CHPR1_MSK GENMASK(23, 22)
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/include/linux/spi/
A Dsh_msiof.h29 #define SIMDR1_SYNCMD GENMASK(29, 28) /* SYNC Mode */
37 #define SIMDR1_FLD GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
41 #define SITMDR1_SYNCCH GENMASK(27, 26) /* Sync Signal Channel Select */
45 #define SIMDR2_GRP GENMASK(31, 30) /* Group Count */
46 #define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */
51 #define SIMDR3_BITLEN2 GENMASK(28, 24) /* Data Size (8-32 bits) */
55 #define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */
62 #define SICTR_RSCKIZ GENMASK(29, 28) /* Receive Clock Polarity Select */
79 #define SIFCTR_TFWM GENMASK(31, 29) /* Transmit FIFO Watermark */
88 #define SIFCTR_TFUA GENMASK(28, 20) /* Transmit FIFO Usable Area */
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/include/linux/dsa/
A Dtag_qca.h14 #define QCA_HDR_RECV_VERSION GENMASK(15, 14)
15 #define QCA_HDR_RECV_PRIORITY GENMASK(13, 11)
16 #define QCA_HDR_RECV_TYPE GENMASK(10, 6)
18 #define QCA_HDR_RECV_SOURCE_PORT GENMASK(2, 0)
25 #define QCA_HDR_XMIT_VERSION GENMASK(15, 14)
26 #define QCA_HDR_XMIT_PRIORITY GENMASK(13, 11)
27 #define QCA_HDR_XMIT_CONTROL GENMASK(10, 8)
29 #define QCA_HDR_XMIT_DP_BIT GENMASK(6, 0)
56 #define QCA_HDR_MGMT_SEQ_NUM GENMASK(31, 0) /* 63, 32 */
59 #define QCA_HDR_MGMT_LENGTH GENMASK(23, 20) /* 23, 20 */
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/include/soc/rockchip/
A Drk3588_grf.h6 #define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
7 #define RK3588_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
8 #define RK3588_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18)
9 #define RK3588_PMUGRF_OS_REG2_CH_INFO GENMASK(29, 28)
12 #define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
13 #define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)
A Drk3568_grf.h6 #define RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
7 #define RK3568_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2)
10 #define RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
11 #define RK3568_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)
/include/linux/soundwire/
A Dsdw_registers.h13 #define SDW_REGADDR GENMASK(14, 0)
14 #define SDW_SCP_ADDRPAGE2_MASK GENMASK(22, 15)
15 #define SDW_SCP_ADDRPAGE1_MASK GENMASK(30, 23)
74 #define SDW_SCP_INT1_PORT0_3 GENMASK(6, 3)
338 (((ent) & GENMASK(5, 0)) << 7) | \
340 (((ctl) & GENMASK(3, 0)) << 3) | \
341 (((ch) & GENMASK(5, 3)) << 12) | \
342 ((ch) & GENMASK(2, 0)))
346 FIELD_GET(GENMASK(12, 7), (reg)))
348 FIELD_GET(GENMASK(6, 3), (reg)))
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A Dsdw_intel.h25 #define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0)
32 #define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
34 #define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
47 #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
63 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
64 #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
65 #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
73 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
74 #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
106 #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
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/include/linux/irqchip/
A Darm-gic-v5.h19 #define GICV5_HWIRQ_ID GENMASK(23, 0)
20 #define GICV5_HWIRQ_TYPE GENMASK(31, 29)
81 #define GICV5_IRS_IDR2_ID_BITS GENMASK(4, 0)
104 #define GICV5_IRS_CR1_IC GENMASK(5, 4)
105 #define GICV5_IRS_CR1_OC GENMASK(3, 2)
106 #define GICV5_IRS_CR1_SH GENMASK(1, 0)
115 #define GICV5_IRS_SPI_SELR_ID GENMASK(23, 0)
170 #define GICV5_ITS_IDR1_L2SZ GENMASK(10, 8)
187 #define GICV5_ITS_CR1_IC GENMASK(5, 4)
188 #define GICV5_ITS_CR1_OC GENMASK(3, 2)
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/include/linux/soc/mediatek/
A Dinfracfg.h77 #define MT8195_TOP_AXI_PROT_EN_MFG1_2ND GENMASK(22, 21)
79 #define MT8195_TOP_AXI_PROT_EN_1_MFG1 GENMASK(20, 19)
82 #define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND GENMASK(6, 5)
90 #define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1 GENMASK(8, 5)
150 #define MT8192_TOP_AXI_PROT_EN_MFG1 GENMASK(22, 21)
157 #define MT8192_TOP_AXI_PROT_EN_2_MFG1 GENMASK(6, 5)
223 #define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2 (GENMASK(19, 17) | GENMASK(26, 25))
236 #define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1 (GENMASK(18, 17) | GENMASK(21, 20))
325 #define MT8186_TOP_AXI_PROT_EN_DIS_STEP2 (GENMASK(2, 1) | GENMASK(11, 10))
372 #define MT8183_TOP_AXI_PROT_EN_1_MFG GENMASK(21, 19)
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/include/media/drv-intf/
A Dcx25840.h100 #define CX25840_VCONFIG_FMT_MASK GENMASK(2, 0)
103 #define CX25840_VCONFIG_FMT_VIP11 GENMASK(1, 0)
107 #define CX25840_VCONFIG_RES_MASK GENMASK(4, 3)
112 #define CX25840_VCONFIG_VBIRAW_MASK GENMASK(6, 5)
117 #define CX25840_VCONFIG_ANCDATA_MASK GENMASK(8, 7)
122 #define CX25840_VCONFIG_TASKBIT_MASK GENMASK(10, 9)
127 #define CX25840_VCONFIG_ACTIVE_MASK GENMASK(12, 11)
132 #define CX25840_VCONFIG_VALID_MASK GENMASK(14, 13)
137 #define CX25840_VCONFIG_HRESETW_MASK GENMASK(16, 15)
148 #define CX25840_VCONFIG_DCMODE_MASK GENMASK(20, 19)
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/include/sound/sof/ipc4/
A Dheader.h161 #define SOF_IPC4_MSG_TYPE_MASK GENMASK(28, 24)
171 #define SOF_IPC4_GLB_PIPE_INSTANCE_MASK GENMASK(23, 16)
179 #define SOF_IPC4_GLB_PIPE_MEM_SIZE_MASK GENMASK(10, 0)
196 #define SOF_IPC4_GLB_PIPE_STATE_MASK GENMASK(15, 0)
327 #define SOF_IPC4_MOD_INSTANCE_MASK GENMASK(23, 16)
331 #define SOF_IPC4_MOD_ID_MASK GENMASK(15, 0)
340 #define SOF_IPC4_MOD_EXT_PPL_ID_MASK GENMASK(23, 16)
344 #define SOF_IPC4_MOD_EXT_CORE_ID_MASK GENMASK(27, 24)
373 #define SOF_IPC4_MOD_EXT_MSG_SIZE_MASK GENMASK(19, 0)
474 #define SOF_IPC4_REPLY_STATUS GENMASK(23, 0)
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/include/linux/
A Dpxa2xx_ssp.h49 #define SSCR0_DSS GENMASK(3, 0) /* Data Size Select (mask) */
51 #define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */
64 #define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */
88 #define SSSR_TFL_MASK GENMASK(11, 8) /* Transmit FIFO Level mask */
89 #define SSSR_RFL_MASK GENMASK(15, 12) /* Receive FIFO Level mask */
91 #define SSCR1_TFT GENMASK(9, 6) /* Transmit FIFO Threshold (mask) */
93 #define SSCR1_RFT GENMASK(13, 10) /* Receive FIFO Threshold (mask) */
99 #define CE4100_SSSR_TFL_MASK GENMASK(9, 8) /* Transmit FIFO Level mask */
113 #define QUARK_X1000_SSCR0_FRF GENMASK(6, 5) /* FRame Format (mask) */
193 #define SFIFOL_TFL_MASK GENMASK(15, 0) /* Transmit FIFO Level mask */
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