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Searched refs:tx (Results 1 – 25 of 31) sorted by relevance

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/include/linux/
A Dasync_tx.h88 static inline void async_tx_issue_pending(struct dma_async_tx_descriptor *tx) in async_tx_issue_pending() argument
90 if (likely(tx)) { in async_tx_issue_pending()
91 struct dma_chan *chan = tx->chan; in async_tx_issue_pending()
112 static inline void async_tx_issue_pending(struct dma_async_tx_descriptor *tx) in async_tx_issue_pending() argument
147 struct dma_async_tx_descriptor *tx, in init_async_submit() argument
152 args->depend_tx = tx; in init_async_submit()
158 void async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx,
202 void async_tx_quiesce(struct dma_async_tx_descriptor **tx);
A Ddmaengine.h639 tx->unmap = unmap; in dma_set_unmap()
662 if (!tx->unmap) in dma_descriptor_unmap()
665 dmaengine_unmap_put(tx->unmap); in dma_descriptor_unmap()
666 tx->unmap = NULL; in dma_descriptor_unmap()
1403 tx->flags |= DMA_CTRL_ACK; in async_tx_ack()
1408 tx->flags &= ~DMA_CTRL_ACK; in async_tx_clear_ack()
1416 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) argument
1423 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) argument
1436 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) argument
1592 tx->flags |= DMA_CTRL_REUSE; in dmaengine_desc_set_reuse()
[all …]
A Dserial.h41 __u32 cts, dsr, rng, dcd, tx, rx; member
A Dpeci.h106 } rx, tx; member
A Dposix-clock.h42 int (*clock_adjtime)(struct posix_clock *pc, struct __kernel_timex *tx);
A Dlinkmode.h83 void linkmode_set_pause(unsigned long *advertisement, bool tx, bool rx);
A Dmoxtet.h43 u8 tx[TURRIS_MOX_MAX_MODULES]; member
A Dwwan.h65 int (*tx)(struct wwan_port *port, struct sk_buff *skb); member
A Dserial_core.h419 __u32 tx; member
846 up->icount.tx += chars; in uart_xmit_advance()
855 up->icount.tx += chars; in uart_fifo_out()
867 up->icount.tx += chars; in uart_fifo_get()
910 for (; (for_test) && (tx_ready); (for_post), __port->icount.tx++) { \
/include/soc/tegra/
A Divc.h23 } rx, tx; member
97 dma_addr_t rx_phys, const struct iosys_map *tx, dma_addr_t tx_phys,
A Dbpmp.h117 } tx; member
/include/uapi/linux/
A Datm_eni.h15 int tx,rx; /* values are in percent and must be > 100 */ member
A Dif_xdp.h68 struct xdp_ring_offset tx; member
A Dserial.h105 int rx, tx; member
A Datmdev.h35 __HANDLE_ITEM(tx); /* TX okay */ \
A Dsynclink.h214 __u32 cts, dsr, rng, dcd, tx, rx; member
/include/linux/spi/
A Daltera.h40 const unsigned char *tx; member
/include/linux/mfd/
A Dipaq-micro.h114 struct ipaq_micro_txdev tx; /* transmit ISR state */ member
/include/linux/soc/ti/
A Dknav_dma.h125 struct knav_dma_tx_cfg tx; member
/include/trace/events/
A Dafs.h1662 TP_PROTO(struct afs_server *server, bool tx, struct afs_endpoint_state *estate,
1665 TP_ARGS(server, tx, estate, addr_index, error, abort_code, rtt_us),
1670 __field(bool, tx)
1682 __entry->tx = tx;
1692 __entry->server, __entry->tx ? "tx" : "rx", __entry->estate,
1698 TP_PROTO(struct afs_vlserver *server, bool tx, struct afs_addr_list *alist,
1701 TP_ARGS(server, tx, alist, addr_index, error, abort_code, rtt_us),
1705 __field(bool, tx)
1716 __entry->tx = tx;
1726 __entry->server, __entry->tx ? "tx" : "rx", __entry->addr_index,
/include/net/
A Dxdp_sock.h65 struct xsk_queue *tx ____cacheline_aligned_in_smp;
A Dnetdev_queues.h105 struct netdev_queue_stats_tx *tx);
A Dtls.h239 struct cipher_context tx; member
/include/acpi/
A Dprocessor.h200 int tx; /* throttle level */ member
/include/linux/iio/imu/
A Dadis.h157 u8 tx[10] __aligned(IIO_DMA_MINALIGN);

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