Searched refs:level (Results 1 – 7 of 7) sorted by relevance
| /mm/ |
| A D | vmpressure.c | 152 enum vmpressure_levels level; member
158 const enum vmpressure_levels level, in vmpressure_event() argument
170 if (level < ev->level) in vmpressure_event()
185 enum vmpressure_levels level; in vmpressure_work_fn() local
209 level = vmpressure_calc_level(scanned, reclaimed); in vmpressure_work_fn()
292 enum vmpressure_levels level; in vmpressure() local
308 level = vmpressure_calc_level(scanned, reclaimed); in vmpressure()
310 if (level > VMPRESSURE_LOW) { in vmpressure()
380 enum vmpressure_levels level; in vmpressure_register_event() local
394 level = ret; in vmpressure_register_event()
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| A D | rmap.c | 1246 enum rmap_level level, int *nr_pmdmapped) in __folio_add_rmap() argument
1254 switch (level) { in __folio_add_rmap()
1285 if (level == RMAP_LEVEL_PMD && first) in __folio_add_rmap()
1304 if (level == RMAP_LEVEL_PMD) in __folio_add_rmap()
1444 switch (level) { in __folio_add_anon_rmap()
1614 enum rmap_level level) in __folio_add_file_rmap() argument
1688 enum rmap_level level) in __folio_remove_rmap() argument
1696 switch (level) { in __folio_remove_rmap()
1731 if (level == RMAP_LEVEL_PMD && last) in __folio_remove_rmap()
1751 if (level == RMAP_LEVEL_PMD) in __folio_remove_rmap()
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| A D | internal.h | 1166 #define mminit_dprintk(level, prefix, fmt, arg...) \ argument
1168 if (level < mminit_loglevel) { \
1169 if (level <= MMINIT_WARNING) \
1180 static inline void mminit_dprintk(enum mminit_level level, in mminit_dprintk() argument
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| A D | pagewalk.c | 901 fw->level = FW_LEVEL_PUD; in folio_walk_start()
936 fw->level = FW_LEVEL_PMD; in folio_walk_start()
976 fw->level = FW_LEVEL_PTE; in folio_walk_start()
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| A D | slub.c | 945 static void print_section(char *level, char *text, u8 *addr, in print_section() argument
949 print_hex_dump(level, text, DUMP_PREFIX_ADDRESS, in print_section()
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| A D | Kconfig | 430 # Architecture platforms which require a two level mem_section in SPARSEMEM
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| /mm/damon/ |
| A D | Kconfig | 10 for performance-centric DRAM level memory management.
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