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Searched refs:reg_offset (Results 1 – 24 of 24) sorted by relevance

/sound/soc/sof/amd/
A Dacp-stream.c41 stream->reg_offset = PTE_GRP1_OFFSET; in acp_dsp_stream_config()
47 stream->reg_offset = PTE_GRP2_OFFSET; in acp_dsp_stream_config()
53 stream->reg_offset = PTE_GRP3_OFFSET; in acp_dsp_stream_config()
59 stream->reg_offset = PTE_GRP4_OFFSET; in acp_dsp_stream_config()
65 stream->reg_offset = PTE_GRP5_OFFSET; in acp_dsp_stream_config()
71 stream->reg_offset = PTE_GRP6_OFFSET; in acp_dsp_stream_config()
77 stream->reg_offset = PTE_GRP7_OFFSET; in acp_dsp_stream_config()
83 stream->reg_offset = PTE_GRP8_OFFSET; in acp_dsp_stream_config()
93 offsetof(struct scratch_reg_conf, reg_offset); in acp_dsp_stream_config()
98 phy_addr_offset, stream->reg_offset); in acp_dsp_stream_config()
A Dacp-trace.c60 dtrace_params->buffer.phy_addr = stream->reg_offset; in acp_sof_trace_init()
A Dacp.h181 unsigned int reg_offset[8]; member
196 unsigned int reg_offset; member
A Dacp-pcm.c40 platform_params->phy_addr = stream->reg_offset; in acp_pcm_hw_params()
A Dacp.c364 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; in memcpy_from_scratch() local
368 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i); in memcpy_from_scratch()
373 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; in memcpy_to_scratch() local
377 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]); in memcpy_to_scratch()
/sound/soc/fsl/
A Dfsl_sai.c1642 .reg_offset = 0,
1653 .reg_offset = 0,
1664 .reg_offset = 8,
1675 .reg_offset = 8,
1686 .reg_offset = 0,
1696 .reg_offset = 8,
1707 .reg_offset = 8,
1718 .reg_offset = 8,
1730 .reg_offset = 8,
1741 .reg_offset = 8,
[all …]
A Dfsl_sai.h240 unsigned int reg_offset; member
/sound/soc/tegra/
A Dtegra210_amx.c65 regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL + amx->soc_data->reg_offset, in tegra210_amx_write_map_ram()
71 regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_DATA + amx->soc_data->reg_offset, in tegra210_amx_write_map_ram()
191 amx->soc_data->reg_offset), in tegra210_amx_in_hw_params()
193 regmap_write(amx->regmap, TEGRA210_AMX_CYA + amx->soc_data->reg_offset, 1); in tegra210_amx_in_hw_params()
691 .reg_offset = TEGRA210_AMX_AUTO_DISABLE_OFFSET,
700 .reg_offset = TEGRA210_AMX_AUTO_DISABLE_OFFSET,
709 .reg_offset = TEGRA264_AMX_AUTO_DISABLE_OFFSET,
A Dtegra210_amx.h103 unsigned int reg_offset; member
/sound/pci/
A Dintel8x0m.c140 unsigned long reg_offset; /* offset to bmaddr */ member
370 unsigned long port = ichdev->reg_offset; in snd_intel8x0m_setup_periods()
420 unsigned long port = ichdev->reg_offset; in snd_intel8x0m_update()
509 unsigned long port = ichdev->reg_offset; in snd_intel8x0m_pcm_trigger()
545 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift; in snd_intel8x0m_pcm_pointer()
937 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); in snd_intel8x0m_chip_init()
940 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); in snd_intel8x0m_chip_init()
956 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); in snd_intel8x0m_free()
959 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); in snd_intel8x0m_free()
1088 ichdev->reg_offset = tbl[i].offset; in snd_intel8x0m_init()
[all …]
A Dintel8x0.c310 unsigned long reg_offset; /* offset to bmaddr */ member
640 unsigned long port = ichdev->reg_offset; in snd_intel8x0_setup_periods()
692 unsigned long port = ichdev->reg_offset; in snd_intel8x0_update()
788 unsigned long port = ichdev->reg_offset; in snd_intel8x0_pcm_trigger()
825 unsigned long port = ichdev->reg_offset; in snd_intel8x0_ali_trigger()
998 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); in snd_intel8x0_pcm_pointer()
2612 unsigned long port = ichdev->reg_offset; in intel8x0_resume()
2664 port = ichdev->reg_offset; in intel8x0_measure_ac97_clock()
2680 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); in intel8x0_measure_ac97_clock()
2964 ichdev->reg_offset = tbl[i].offset; in snd_intel8x0_init()
[all …]
A Dvia82xx.c310 unsigned int reg_offset; member
1031 if (chip->spdif_on && viadev->reg_offset == 0x30) in snd_via8233_playback_prepare()
1042 outb(chip->playback_volume[viadev->reg_offset / 0x10][0], in snd_via8233_playback_prepare()
1044 outb(chip->playback_volume[viadev->reg_offset / 0x10][1], in snd_via8233_playback_prepare()
1172 if (chip->spdif_on && viadev->reg_offset == 0x30) { in snd_via82xx_pcm_open()
1176 } else if (chip->dxs_fixed && viadev->reg_offset < 0x40) { in snd_via82xx_pcm_open()
1180 } else if (chip->dxs_src && viadev->reg_offset < 0x40) { in snd_via82xx_pcm_open()
1246 stream = viadev->reg_offset / 0x10; in snd_via8233_playback_open()
1341 stream = viadev->reg_offset / 0x10; in snd_via8233_playback_close()
1411 chip->devs[idx].reg_offset = reg_offset; in init_viadev()
[all …]
A Dvia82xx_modem.c205 unsigned int reg_offset; member
817 static void init_viadev(struct via82xx_modem *chip, int idx, unsigned int reg_offset, in init_viadev() argument
820 chip->devs[idx].reg_offset = reg_offset; in init_viadev()
822 chip->devs[idx].port = chip->port + reg_offset; in init_viadev()
/sound/soc/amd/acp/
A Dacp-legacy-common.c157 physical_addr = stream->reg_offset + MEM_WINDOW_START; in set_acp_pdm_ring_buffer()
222 phy_addr = I2S_SP_TX_MEM_WINDOW_START + stream->reg_offset; in set_acp_i2s_dma_fifo()
230 phy_addr = I2S_SP_RX_MEM_WINDOW_START + stream->reg_offset; in set_acp_i2s_dma_fifo()
241 phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset; in set_acp_i2s_dma_fifo()
249 phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset; in set_acp_i2s_dma_fifo()
260 phy_addr = I2S_HS_TX_MEM_WINDOW_START + stream->reg_offset; in set_acp_i2s_dma_fifo()
268 phy_addr = I2S_HS_RX_MEM_WINDOW_START + stream->reg_offset; in set_acp_i2s_dma_fifo()
A Dacp-i2s.c539 phy_addr = I2S_SP_TX_MEM_WINDOW_START + stream->reg_offset; in acp_i2s_prepare()
551 phy_addr = I2S_SP_RX_MEM_WINDOW_START + stream->reg_offset; in acp_i2s_prepare()
566 phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset; in acp_i2s_prepare()
578 phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset; in acp_i2s_prepare()
593 phy_addr = I2S_HS_TX_MEM_WINDOW_START + stream->reg_offset; in acp_i2s_prepare()
605 phy_addr = I2S_HS_RX_MEM_WINDOW_START + stream->reg_offset; in acp_i2s_prepare()
A Dacp-pdm.c52 physical_addr = stream->reg_offset + MEM_WINDOW_START; in acp_dmic_prepare()
153 stream->reg_offset = ACP_REGION2_OFFSET; in acp_dmic_dai_startup()
A Damd.h183 u32 reg_offset; member
A Dacp-platform.c116 stream->reg_offset = 0x02000000; in config_pte_for_stream()
/sound/soc/codecs/
A Dwm8995.c1800 int reg_offset, ret; in wm8995_set_fll() local
1815 reg_offset = 0; in wm8995_set_fll()
1819 reg_offset = 0x20; in wm8995_set_fll()
1865 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset, in wm8995_set_fll()
1870 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_2 + reg_offset, in wm8995_set_fll()
1874 snd_soc_component_write(component, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); in wm8995_set_fll()
1876 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_4 + reg_offset, in wm8995_set_fll()
1880 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_5 + reg_offset, in wm8995_set_fll()
1887 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset, in wm8995_set_fll()
A Dwm8994.c2210 int reg_offset, ret; in _wm8994_set_fll() local
2219 reg_offset = 0; in _wm8994_set_fll()
2224 reg_offset = 0x20; in _wm8994_set_fll()
2232 reg = snd_soc_component_read(component, WM8994_FLL1_CONTROL_1 + reg_offset); in _wm8994_set_fll()
2288 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset, in _wm8994_set_fll()
2294 + reg_offset); in _wm8994_set_fll()
2322 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_2 + reg_offset, in _wm8994_set_fll()
2326 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_3 + reg_offset, in _wm8994_set_fll()
2334 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_1 + reg_offset, in _wm8994_set_fll()
2337 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset, in _wm8994_set_fll()
[all …]
A Dcs35l45.h457 .reg_offset = (CS35L45_ ## _reg) - CS35L45_IRQ1_EINT_1, \
A Dwcd9335.c4945 .reg_offset = 0,
/sound/soc/renesas/rcar/
A Dgen.c38 unsigned int reg_offset; member
46 .reg_offset = offset, \
198 regf.reg = conf[i].reg_offset; in _rsnd_gen_regmap_init()
/sound/soc/rockchip/
A Drockchip_i2s.c27 u32 reg_offset; member
446 regmap_write(i2s->grf, i2s->pins->reg_offset, val); in rockchip_i2s_hw_params()
643 .reg_offset = 0xe220,

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