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Searched refs:BIT (Results 1 – 25 of 77) sorted by relevance

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/tools/arch/x86/include/asm/
A Dmsr-index.h224 #define L1D_FLUSH BIT(0) /*
326 #define RTIT_CTL_TRACEEN BIT(0)
327 #define RTIT_CTL_CYCLEACC BIT(1)
328 #define RTIT_CTL_OS BIT(2)
329 #define RTIT_CTL_USR BIT(3)
333 #define RTIT_CTL_CR3EN BIT(7)
334 #define RTIT_CTL_TOPA BIT(8)
335 #define RTIT_CTL_MTC_EN BIT(9)
336 #define RTIT_CTL_TSC_EN BIT(10)
337 #define RTIT_CTL_DISRETC BIT(11)
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/tools/perf/util/arm-spe-decoder/
A Darm-spe-pkt-decoder.h119 #define SPE_OP_PKT_IS_OTHER_SVE_OP(v) (((v) & (BIT(7) | BIT(3) | BIT(0))) == 0x8)
132 #define SPE_OP_PKT_AR BIT(4)
133 #define SPE_OP_PKT_EXCL BIT(3)
134 #define SPE_OP_PKT_AT BIT(2)
135 #define SPE_OP_PKT_ST BIT(0)
137 #define SPE_OP_PKT_IS_LDST_SVE(v) (((v) & (BIT(3) | BIT(1))) == 0x8)
139 #define SPE_OP_PKT_SVE_SG BIT(7)
148 #define SPE_OP_PKT_SVE_PRED BIT(2)
149 #define SPE_OP_PKT_SVE_FP BIT(1)
155 #define SPE_OP_PKT_GCS BIT(2)
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A Darm-spe-decoder.c73 if (!(seen_idx & BIT(index))) { in arm_spe_calc_ip()
74 seen_idx |= BIT(index); in arm_spe_calc_ip()
232 if (payload & BIT(EV_L1D_REFILL)) in arm_spe_read_record()
235 if (payload & BIT(EV_L1D_ACCESS)) in arm_spe_read_record()
238 if (payload & BIT(EV_TLB_WALK)) in arm_spe_read_record()
241 if (payload & BIT(EV_TLB_ACCESS)) in arm_spe_read_record()
244 if (payload & BIT(EV_LLC_MISS)) in arm_spe_read_record()
247 if (payload & BIT(EV_LLC_ACCESS)) in arm_spe_read_record()
250 if (payload & BIT(EV_REMOTE_ACCESS)) in arm_spe_read_record()
253 if (payload & BIT(EV_MISPRED)) in arm_spe_read_record()
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A Darm-spe-pkt-decoder.c287 if (payload & BIT(EV_EXCEPTION_GEN)) in arm_spe_pkt_desc_event()
289 if (payload & BIT(EV_RETIRED)) in arm_spe_pkt_desc_event()
291 if (payload & BIT(EV_L1D_ACCESS)) in arm_spe_pkt_desc_event()
293 if (payload & BIT(EV_L1D_REFILL)) in arm_spe_pkt_desc_event()
295 if (payload & BIT(EV_TLB_ACCESS)) in arm_spe_pkt_desc_event()
297 if (payload & BIT(EV_TLB_WALK)) in arm_spe_pkt_desc_event()
299 if (payload & BIT(EV_NOT_TAKEN)) in arm_spe_pkt_desc_event()
301 if (payload & BIT(EV_MISPRED)) in arm_spe_pkt_desc_event()
303 if (payload & BIT(EV_LLC_ACCESS)) in arm_spe_pkt_desc_event()
305 if (payload & BIT(EV_LLC_MISS)) in arm_spe_pkt_desc_event()
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/tools/testing/selftests/kvm/include/riscv/
A Dsbi.h107 #define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0)
108 #define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1)
109 #define SBI_PMU_CFG_FLAG_AUTO_START BIT(2)
110 #define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3)
111 #define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4)
112 #define SBI_PMU_CFG_FLAG_SET_UINH BIT(5)
113 #define SBI_PMU_CFG_FLAG_SET_SINH BIT(6)
114 #define SBI_PMU_CFG_FLAG_SET_MINH BIT(7)
118 #define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1)
121 #define SBI_PMU_STOP_FLAG_RESET BIT(0)
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/tools/testing/selftests/bpf/
A Dxdp_metadata.h20 #ifndef BIT
21 #define BIT(nr) (1 << (nr)) macro
25 #define XDP_CHECKSUM_MAGIC BIT(2)
28 XDP_META_FIELD_TS = BIT(0),
29 XDP_META_FIELD_RSS = BIT(1),
30 XDP_META_FIELD_VLAN_TAG = BIT(2),
/tools/arch/arm64/include/asm/
A Dsysreg.h187 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
190 #define OSLSR_EL1_OSLK BIT(1)
331 #define SYS_PAR_EL1_F BIT(0)
335 #define SYS_PAR_EL1_S BIT(9)
341 #define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
846 #define SCTLR_ELx_C (BIT(2))
847 #define SCTLR_ELx_A (BIT(1))
848 #define SCTLR_ELx_M (BIT(0))
851 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
852 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
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/tools/testing/selftests/kvm/x86/
A Dsev_init2_tests.c92 if (kvm_check_cap(KVM_CAP_VM_TYPES) & BIT(KVM_X86_SW_PROTECTED_VM)) in test_vm_types()
103 &(struct kvm_sev_init){ .flags = BIT(i) }, in test_flags()
134 TEST_ASSERT(have_sev == !!(kvm_check_cap(KVM_CAP_VM_TYPES) & BIT(KVM_X86_SEV_VM)), in main()
138 TEST_REQUIRE(kvm_check_cap(KVM_CAP_VM_TYPES) & BIT(KVM_X86_SEV_VM)); in main()
141 TEST_ASSERT(have_sev_es == !!(kvm_check_cap(KVM_CAP_VM_TYPES) & BIT(KVM_X86_SEV_ES_VM)), in main()
146 TEST_ASSERT(have_snp == !!(kvm_check_cap(KVM_CAP_VM_TYPES) & BIT(KVM_X86_SNP_VM)), in main()
A Dmonitor_mwait_test.c15 MWAIT_QUIRK_DISABLED = BIT(0),
16 MISC_ENABLES_QUIRK_DISABLED = BIT(1),
17 MWAIT_DISABLED = BIT(2),
18 CPUID_DISABLED = BIT(3),
A Dpmu_event_filter_test.c489 #define ALLOW_LOADS BIT(0)
490 #define ALLOW_STORES BIT(1)
491 #define ALLOW_LOADS_STORES BIT(2)
516 INCLUDE_MASKED_ENTRY(LS_DISPATCH, 0xFF, BIT(0)),
544 INCLUDE_MASKED_ENTRY(LS_DISPATCH, ~(BIT(0) | BIT(1)), 0),
787 for (i = 0; i < BIT(nr_fixed_counters); i++) { in __test_fixed_counter_bitmap()
788 bitmap = BIT(i); in __test_fixed_counter_bitmap()
791 TEST_ASSERT_EQ(!!count, !!(bitmap & BIT(idx))); in __test_fixed_counter_bitmap()
795 TEST_ASSERT_EQ(!!count, !(bitmap & BIT(idx))); in __test_fixed_counter_bitmap()
804 TEST_ASSERT_EQ(!!count, !!(bitmap & BIT(idx))); in __test_fixed_counter_bitmap()
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A Dsvm_nested_soft_inject_test.c93 vmcb->control.intercept_exceptions |= BIT(PF_VECTOR) | BIT(UD_VECTOR); in l1_guest_code()
94 vmcb->control.intercept |= BIT(INTERCEPT_NMI) | BIT(INTERCEPT_HLT); in l1_guest_code()
A Dsvm_int_ctl_test.c71 vmcb->control.intercept &= ~(BIT(INTERCEPT_INTR) | BIT(INTERCEPT_VINTR)); in l1_guest_code()
/tools/power/x86/intel-speed-select/
A Disst-core-mbox.c715 req = BIT(16); in mbox_set_pbf_fact_status()
718 req |= BIT(17); in mbox_set_pbf_fact_status()
720 req &= ~BIT(17); in mbox_set_pbf_fact_status()
727 req = BIT(17); in mbox_set_pbf_fact_status()
730 req |= BIT(16); in mbox_set_pbf_fact_status()
732 req &= ~BIT(16); in mbox_set_pbf_fact_status()
850 if (resp & BIT(1)) in mbox_get_clos_information()
855 if (resp & BIT(2)) in mbox_get_clos_information()
869 req = BIT(16); in _write_pm_config()
928 req = req | BIT(1); in mbox_pm_qos_config()
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A Disst-core-tpmi.c128 if (info.valid_mask & BIT(id->punit)) in tpmi_is_punit_valid()
198 ctdp_level->fact_support = info.sst_tf_support & BIT(config_index); in tpmi_get_ctdp_control()
199 ctdp_level->pbf_support = info.sst_bf_support & BIT(config_index); in tpmi_get_ctdp_control()
205 ctdp_level->fact_enabled = !!(info.feature_state & BIT(1)); in tpmi_get_ctdp_control()
206 ctdp_level->pbf_enabled = !!(info.feature_state & BIT(0)); in tpmi_get_ctdp_control()
480 info.feature |= BIT(1); in tpmi_set_pbf_fact_status()
483 info.feature |= BIT(0); in tpmi_set_pbf_fact_status()
485 info.feature &= ~BIT(0); in tpmi_set_pbf_fact_status()
494 info.feature |= BIT(0); in tpmi_set_pbf_fact_status()
497 info.feature |= BIT(1); in tpmi_set_pbf_fact_status()
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/tools/mm/
A Dpage-types.c99 #define BITS_COMPOUND (BIT(COMPOUND_HEAD) | BIT(COMPOUND_TAIL))
476 if ((flags & BIT(ANON)) && (flags & BIT(OWNER_2))) in expand_overloaded_flags()
477 flags ^= BIT(OWNER_2) | BIT(ANON_EXCLUSIVE); in expand_overloaded_flags()
480 if (flags & BIT(SLAB)) { in expand_overloaded_flags()
482 flags ^= BIT(ACTIVE) | BIT(SLUB_FROZEN); in expand_overloaded_flags()
483 if (flags & BIT(ERROR)) in expand_overloaded_flags()
484 flags ^= BIT(ERROR) | BIT(SLUB_DEBUG); in expand_overloaded_flags()
488 if ((flags & (BIT(RECLAIM) | BIT(WRITEBACK))) == BIT(RECLAIM)) in expand_overloaded_flags()
489 flags ^= BIT(RECLAIM) | BIT(READAHEAD); in expand_overloaded_flags()
494 flags |= BIT(FILE); in expand_overloaded_flags()
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/tools/testing/selftests/net/bench/page_pool/
A Dtime_bench.h18 #define TIME_BENCH_LOOP BIT(0)
19 #define TIME_BENCH_TSC BIT(1)
20 #define TIME_BENCH_WALLCLOCK BIT(2)
21 #define TIME_BENCH_PMU BIT(3)
/tools/testing/selftests/net/tcp_ao/lib/
A Daolib.h523 #define TEST_CNT_KEY_GOOD BIT(0)
524 #define TEST_CNT_KEY_BAD BIT(1)
525 #define TEST_CNT_SOCK_GOOD BIT(2)
526 #define TEST_CNT_SOCK_BAD BIT(3)
528 #define TEST_CNT_SOCK_AO_REQUIRED BIT(5)
530 #define TEST_CNT_NS_GOOD BIT(7)
531 #define TEST_CNT_NS_BAD BIT(8)
532 #define TEST_CNT_NS_KEY_NOT_FOUND BIT(9)
533 #define TEST_CNT_NS_AO_REQUIRED BIT(10)
534 #define TEST_CNT_NS_DROPPED_ICMP BIT(11)
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/tools/testing/selftests/kvm/include/arm64/
A Dprocessor.h110 #define PTE_VALID BIT(0)
111 #define PGD_TYPE_TABLE BIT(1)
112 #define PUD_TYPE_TABLE BIT(1)
113 #define PMD_TYPE_TABLE BIT(1)
114 #define PTE_TYPE_PAGE BIT(1)
117 #define PTE_AF BIT(10)
/tools/perf/arch/arm/util/
A Dcs-etm.c504 #ifndef BIT
505 #define BIT(N) (1UL << (N)) macro
520 if (config_opts & BIT(ETM_OPT_CYCACC)) in cs_etmv4_get_config()
521 config |= BIT(ETM4_CFG_BIT_CYCACC); in cs_etmv4_get_config()
523 config |= BIT(ETM4_CFG_BIT_CTXTID); in cs_etmv4_get_config()
524 if (config_opts & BIT(ETM_OPT_TS)) in cs_etmv4_get_config()
525 config |= BIT(ETM4_CFG_BIT_TS); in cs_etmv4_get_config()
527 config |= BIT(ETM4_CFG_BIT_RETSTK); in cs_etmv4_get_config()
529 config |= BIT(ETM4_CFG_BIT_VMID) | in cs_etmv4_get_config()
530 BIT(ETM4_CFG_BIT_VMID_OPT); in cs_etmv4_get_config()
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/tools/testing/selftests/kvm/
A Dset_memory_region_test.c358 if (kvm_check_cap(KVM_CAP_VM_TYPES) & BIT(KVM_X86_SW_PROTECTED_VM)) in test_invalid_memory_region_flags()
368 if ((supported_flags & BIT(i)) && !(v2_only_flags & BIT(i))) in test_invalid_memory_region_flags()
371 r = __vm_set_user_memory_region(vm, 0, BIT(i), in test_invalid_memory_region_flags()
375 "KVM_SET_USER_MEMORY_REGION should have failed on v2 only flag 0x%lx", BIT(i)); in test_invalid_memory_region_flags()
377 if (supported_flags & BIT(i)) in test_invalid_memory_region_flags()
380 r = __vm_set_user_memory_region2(vm, 0, BIT(i), in test_invalid_memory_region_flags()
383 "KVM_SET_USER_MEMORY_REGION2 should have failed on unsupported flag 0x%lx", BIT(i)); in test_invalid_memory_region_flags()
630 (kvm_check_cap(KVM_CAP_VM_TYPES) & BIT(KVM_X86_SW_PROTECTED_VM))) { in main()
/tools/testing/selftests/kvm/riscv/
A Dsbi_pmu_test.c25 #define PMU_SNAPSHOT_GPA_BASE BIT(30)
37 #define SBI_PMU_TEST_BASIC BIT(0)
38 #define SBI_PMU_TEST_EVENTS BIT(1)
39 #define SBI_PMU_TEST_SNAPSHOT BIT(2)
40 #define SBI_PMU_TEST_OVERFLOW BIT(3)
171 csr_clear(CSR_SIP, BIT(IRQ_PMU_OVF)); in guest_irq_handler()
189 GUEST_ASSERT(BIT(ret.value) & counter_mask_available); in get_counter_index()
221 counter_mask_available |= BIT(i); in update_counter_info()
489 if (counter_mask_available & (BIT(i))) in test_pmu_events_snaphost()
507 csr_set(CSR_IE, BIT(IRQ_PMU_OVF)); in test_pmu_events_overflow()
/tools/testing/selftests/kvm/include/x86/
A Dhyperv.h230 #define HV_FLUSH_ALL_PROCESSORS BIT(0)
231 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1)
232 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2)
233 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3)
249 #define HV_HYPERCALL_FAST_BIT BIT(16)
A Devmcs.h219 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0)
220 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1)
221 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2)
222 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3)
223 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4)
224 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5)
225 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6)
226 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7)
227 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8)
228 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9)
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/tools/include/vdso/
A Dbits.h7 #define BIT(nr) (UL(1) << (nr)) macro
/tools/testing/selftests/sysctl/
A Dsysctl.sh633 BIT=$((RANDOM % 1024))
636 TEST_STR=$BIT
642 BIT=$((BIT + $((2 + RANDOM % 10))))
645 TEST_STR="${TEST_STR},${BIT}"
649 RANGE_END=$((BIT + $((1 + RANDOM % 10))))
651 BIT=$RANGE_END

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