Home
last modified time | relevance | path

Searched refs:BIT_ULL (Results 1 – 25 of 32) sorted by relevance

12

/tools/testing/selftests/kvm/include/x86/
A Dpmu.h28 #define ARCH_PERFMON_EVENTSEL_USR BIT_ULL(16)
29 #define ARCH_PERFMON_EVENTSEL_OS BIT_ULL(17)
32 #define ARCH_PERFMON_EVENTSEL_INT BIT_ULL(20)
39 #define INTEL_RDPMC_METRICS BIT_ULL(29)
40 #define INTEL_RDPMC_FIXED BIT_ULL(30)
41 #define INTEL_RDPMC_FAST BIT_ULL(31)
46 #define FIXED_PMC_KERNEL BIT_ULL(0)
47 #define FIXED_PMC_USER BIT_ULL(1)
48 #define FIXED_PMC_ANYTHREAD BIT_ULL(2)
49 #define FIXED_PMC_ENABLE_PMI BIT_ULL(3)
[all …]
A Dmce.h9 #define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */
10 #define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */
11 #define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */
12 #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
21 #define MCI_CTL2_CMCI_EN BIT_ULL(30)
A Dprocessor.h73 #define XFEATURE_MASK_FP BIT_ULL(0)
74 #define XFEATURE_MASK_SSE BIT_ULL(1)
75 #define XFEATURE_MASK_YMM BIT_ULL(2)
76 #define XFEATURE_MASK_BNDREGS BIT_ULL(3)
77 #define XFEATURE_MASK_BNDCSR BIT_ULL(4)
78 #define XFEATURE_MASK_OPMASK BIT_ULL(5)
80 #define XFEATURE_MASK_Hi16_ZMM BIT_ULL(7)
81 #define XFEATURE_MASK_PT BIT_ULL(8)
82 #define XFEATURE_MASK_PKRU BIT_ULL(9)
83 #define XFEATURE_MASK_PASID BIT_ULL(10)
[all …]
A Dsvm.h159 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
160 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
/tools/arch/x86/include/asm/
A Dmsr-index.h285 #define LBR_INFO_IN_TX BIT_ULL(62)
286 #define LBR_INFO_ABORT BIT_ULL(61)
341 #define RTIT_CTL_NOTNT BIT_ULL(55)
513 #define CET_SHSTK_EN BIT_ULL(0)
514 #define CET_WRSS_EN BIT_ULL(1)
515 #define CET_ENDBR_EN BIT_ULL(2)
516 #define CET_LEG_IW_EN BIT_ULL(3)
517 #define CET_NO_TRACK_EN BIT_ULL(4)
519 #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))
520 #define CET_SUPPRESS BIT_ULL(10)
[all …]
/tools/testing/selftests/kvm/x86/
A Dhwcr_msr_test.c13 const uint64_t ignored = BIT_ULL(3) | BIT_ULL(6) | BIT_ULL(8); in test_hwcr_bit()
14 const uint64_t valid = BIT_ULL(18) | BIT_ULL(24); in test_hwcr_bit()
16 uint64_t val = BIT_ULL(bit); in test_hwcr_bit()
A Dvmx_msrs_test.c24 vcpu_set_msr(vcpu, msr_index, val & ~BIT_ULL(bit)); in vmx_fixed1_msr_test()
38 vcpu_set_msr(vcpu, msr_index, val | BIT_ULL(bit)); in vmx_fixed0_msr_test()
55 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55)); in vmx_save_restore_msrs_test()
58 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | in vmx_save_restore_msrs_test()
59 BIT_ULL(15) | BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30)); in vmx_save_restore_msrs_test()
A Dvmx_pmu_caps_test.c71 guest_test_perf_capabilities_gp(current_val ^ BIT_ULL(i)); in guest_code()
113 host_cap.capabilities ^ BIT_ULL(i)); in KVM_ONE_VCPU_TEST()
115 host_cap.capabilities ^ BIT_ULL(i)); in KVM_ONE_VCPU_TEST()
135 vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, BIT_ULL(bit)); in KVM_ONE_VCPU_TEST()
137 host_cap.capabilities & ~BIT_ULL(bit)); in KVM_ONE_VCPU_TEST()
158 host_cap.capabilities ^ BIT_ULL(bit)); in KVM_ONE_VCPU_TEST()
160 host_cap.capabilities & BIT_ULL(bit) ? "Setting" : "Clearing", in KVM_ONE_VCPU_TEST()
161 BIT_ULL(bit), bit); in KVM_ONE_VCPU_TEST()
227 r = _vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, BIT_ULL(i)); in KVM_ONE_VCPU_TEST()
229 i, BIT_ULL(i)); in KVM_ONE_VCPU_TEST()
A Dhyperv_tlb_flush.c273 flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_2 / 64); in sender_guest_code()
274 flush_ex->hv_vp_set.bank_contents[0] = BIT_ULL(WORKER_VCPU_ID_2 % 64); in sender_guest_code()
288 flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_2 / 64); in sender_guest_code()
289 flush_ex->hv_vp_set.bank_contents[0] = BIT_ULL(WORKER_VCPU_ID_2 % 64); in sender_guest_code()
306 flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_2 / 64) | in sender_guest_code()
307 BIT_ULL(WORKER_VCPU_ID_1 / 64); in sender_guest_code()
325 BIT_ULL(WORKER_VCPU_ID_2 / 64); in sender_guest_code()
432 flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_2 / 64); in sender_guest_code()
448 flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_2 / 64); in sender_guest_code()
468 BIT_ULL(WORKER_VCPU_ID_1 / 64); in sender_guest_code()
[all …]
A Dsev_init2_tests.c112 if (!(supported_features & BIT_ULL(i))) in test_features()
114 &(struct kvm_sev_init){ .vmsa_features = BIT_ULL(i) }, in test_features()
116 else if (KNOWN_FEATURES & BIT_ULL(i)) in test_features()
118 &(struct kvm_sev_init){ .vmsa_features = BIT_ULL(i) }); in test_features()
A Dxcr0_cpuid_test.c93 if (supported_xcr0 & BIT_ULL(i)) in guest_code()
96 vector = xsetbv_safe(0, supported_xcr0 | BIT_ULL(i)); in guest_code()
99 BIT_ULL(i), supported_xcr0, vector); in guest_code()
A Dnested_emulation_test.c64 vmcb->control.intercept |= BIT_ULL(INTERCEPT_SHUTDOWN) | in guest_code()
65 BIT_ULL(INTERCEPT_PAUSE) | in guest_code()
66 BIT_ULL(INTERCEPT_HLT); in guest_code()
A Dnested_exceptions_test.c50 #define INTERCEPT_SS (BIT_ULL(SS_VECTOR))
51 #define INTERCEPT_SS_DF (INTERCEPT_SS | BIT_ULL(DF_VECTOR))
52 #define INTERCEPT_SS_GP_DF (INTERCEPT_SS_DF | BIT_ULL(GP_VECTOR))
98 ctrl->intercept |= BIT_ULL(INTERCEPT_SHUTDOWN); in l1_svm_code()
A Duserspace_msr_exit_test.c719 cap.args[0] = BIT_ULL(i); in run_user_space_msr_flag_test()
721 BIT_ULL(i), KVM_MSR_EXIT_REASON_VALID_MASK); in run_user_space_msr_flag_test()
748 filter.flags = BIT_ULL(i); in run_msr_filter_flag_test()
750 BIT_ULL(i), KVM_MSR_FILTER_VALID_MASK); in run_msr_filter_flag_test()
756 filter.ranges[0].flags = BIT_ULL(i); in run_msr_filter_flag_test()
758 BIT_ULL(i), KVM_MSR_FILTER_RANGE_VALID_MASK); in run_msr_filter_flag_test()
A Dsmaller_maxphyaddr_emulation_test.c77 *pte |= BIT_ULL(MAXPHYADDR); in main()
A Dpmu_counters_test.c280 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(i)); in guest_test_arch_event()
518 if (i >= nr_fixed_counters && !(supported_bitmask & BIT_ULL(i))) { in guest_test_fixed_counters()
A Dstate_test.c192 wrmsr(MSR_IA32_BNDCFGS, BIT_ULL(0)); in guest_code()
/tools/testing/selftests/mm/
A Dvm_util.h12 #define BIT_ULL(nr) (1ULL << (nr)) macro
13 #define PM_SOFT_DIRTY BIT_ULL(55)
14 #define PM_MMAP_EXCLUSIVE BIT_ULL(56)
15 #define PM_UFFD_WP BIT_ULL(57)
16 #define PM_GUARD_REGION BIT_ULL(58)
17 #define PM_FILE BIT_ULL(61)
18 #define PM_SWAP BIT_ULL(62)
19 #define PM_PRESENT BIT_ULL(63)
A Duffd-unit-tests.c17 #define MEM_ANON BIT_ULL(0)
18 #define MEM_SHMEM BIT_ULL(1)
19 #define MEM_SHMEM_PRIVATE BIT_ULL(2)
20 #define MEM_HUGETLB BIT_ULL(3)
21 #define MEM_HUGETLB_PRIVATE BIT_ULL(4)
156 uffdio_api.features = BIT_ULL(63); in test_uffd_api()
171 uffdio_api.features = BIT_ULL(0); in test_uffd_api()
1461 uint64_t ioctls = 0, expected = BIT_ULL(_UFFDIO_WAKE); in do_register_ioctls_test()
1485 expected |= BIT_ULL(_UFFDIO_COPY); in do_register_ioctls_test()
1487 expected |= BIT_ULL(_UFFDIO_WRITEPROTECT); in do_register_ioctls_test()
[all …]
/tools/testing/selftests/kvm/include/loongarch/
A Dprocessor.h59 #define _PAGE_VALID BIT_ULL(_PAGE_VALID_SHIFT)
60 #define _PAGE_PRESENT BIT_ULL(_PAGE_PRESENT_SHIFT)
61 #define _PAGE_WRITE BIT_ULL(_PAGE_WRITE_SHIFT)
62 #define _PAGE_DIRTY BIT_ULL(_PAGE_DIRTY_SHIFT)
67 #define _CACHE_CC BIT_ULL(_CACHE_SHIFT)
76 #define CSR_CRMD_PG BIT_ULL(CSR_CRMD_PG_SHIFT)
78 #define CSR_CRMD_IE BIT_ULL(CSR_CRMD_IE_SHIFT)
/tools/include/vdso/
A Dbits.h8 #define BIT_ULL(nr) (ULL(1) << (nr)) macro
/tools/testing/selftests/kvm/include/s390/
A Dprocessor.h26 #define PAGE_SIZE BIT_ULL(PAGE_SHIFT)
/tools/perf/util/arm-spe-decoder/
A Darm-spe-pkt-decoder.h76 #define SPE_ADDR_PKT_GET_NS(v) (((v) & BIT_ULL(63)) >> 63)
78 #define SPE_ADDR_PKT_GET_CH(v) (((v) & BIT_ULL(62)) >> 62)
/tools/include/linux/
A Dbits.h69 #define BIT_TYPE(type, nr) ((type)(BIT_INPUT_CHECK(type, nr) + BIT_ULL(nr)))
/tools/arch/arm64/include/asm/
A Dsysreg.h355 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
357 (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
359 (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))

Completed in 63 milliseconds

12