| /tools/perf/arch/x86/util/ |
| A D | mem-events.c | 13 E("ldlat-loads", "%s/mem-loads,ldlat=%u/P", "mem-loads", true, 0),
14 E("ldlat-stores", "%s/mem-stores/P", "mem-stores", false, 0),
15 E(NULL, NULL, NULL, false, 0),
20 E("ldlat-stores", "%s/mem-stores/P", "mem-stores", false, 0),
21 E(NULL, NULL, NULL, false, 0),
25 E(NULL, NULL, NULL, false, 0),
26 E(NULL, NULL, NULL, false, 0),
27 E("mem-ldst", "%s//", NULL, false, 0),
31 E(NULL, NULL, NULL, false, 0),
32 E(NULL, NULL, NULL, false, 0),
[all …]
|
| /tools/testing/selftests/bpf/progs/ |
| A D | btf_dump_test_case_namespacing.c | 24 enum E { enum
28 typedef enum E E; typedef
59 enum E _5; in f()
60 E _6; in f()
|
| A D | test_global_func9.c | 23 enum E { enum
53 __noinline int qux(enum E *e) in qux()
116 enum E e = E_ITEM; in global_func9()
|
| A D | btf_dump_test_case_syntax.c | 17 E = 0, enumerator
|
| /tools/perf/arch/arm64/util/ |
| A D | mem-events.c | 6 #define E(t, n, s, l, a) { .tag = t, .name = n, .event_name = s, .ldlat = l, .aux_event = a } macro
9 …E("spe-load", "%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=0,min_latency=%u/", NULL, tru…
10 E("spe-store", "%s/ts_enable=1,pa_enable=1,load_filter=0,store_filter=1/", NULL, false, 0),
11 …E("spe-ldst", "%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=%u/", NULL, tru…
|
| /tools/perf/arch/powerpc/util/ |
| A D | mem-events.c | 6 #define E(t, n, s, l, a) { .tag = t, .name = n, .event_name = s, .ldlat = l, .aux_event = a } macro
9 E("ldlat-loads", "%s/mem-loads/", "mem-loads", false, 0),
10 E("ldlat-stores", "%s/mem-stores/", "mem-stores", false, 0),
11 E(NULL, NULL, NULL, false, 0),
|
| /tools/perf/pmu-events/arch/x86/ |
| A D | mapfile.csv | 22 GenuineIntel-6-3E,v24,ivytown,core
28 GenuineIntel-6-2E,v4,nehalemex,core
35 GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core
|
| /tools/testing/selftests/powerpc/benchmarks/ |
| A D | futex_bench.c | 18 #define futex(A, B, C, D, E, F) syscall(__NR_futex, A, B, C, D, E, F) argument
|
| /tools/memory-model/Documentation/ |
| A D | references.txt | 51 o Shaked Flur, Kathryn E. Gray, Christopher Pulte, Susmit
59 Luc Maranget, Kathryn E. Gray, Ali Sezgin, Mark Batty, and Peter
76 Lustig, Luc Maranget, Paul E. McKenney, Andrea Parri, Nicholas
82 Lustig, Luc Maranget, Paul E. McKenney, Andrea Parri, Nicholas
87 o Jade Alglave, Luc Maranget, Paul E. McKenney, Andrea Parri, and
94 o Jade Alglave, Luc Maranget, Paul E. McKenney, Andrea Parri, and
98 o Jade Alglave, Luc Maranget, Paul E. McKenney, Andrea Parri, and
102 o Jade Alglave, Luc Maranget, Paul E. McKenney, Andrea Parri, and
128 o Paul E. McKenney, Ulrich Weigand, Andrea Parri, and Boqun
|
| A D | explanation.txt | 894 where either X = E or else E ->rf X; or
897 order, where either X = E or else E ->rf X.
1463 The existence of a pb link from E to F implies that E must execute
1465 have propagated to E's CPU before E executed. If E was a store, the
1467 coherence order, contradicting the fact that E ->coe W. If E was a
1606 E ->rcu-gp F means that E and F are in fact the same event,
1610 E ->rcu-rscsi F means that E and F are the rcu_read_unlock()
1642 particular, E ->rcu-order F implies not only that E begins before F
1697 details; the end result is that E ->rb F implies E must execute
1703 and F with E ->rcu-link F ->rcu-order E. Or to put it a third way,
[all …]
|
| /tools/testing/selftests/cgroup/ |
| A D | memcg_protection.m | 15 % E number parent effective protection
20 E = 50 / 1024; variable
52 e = protected * min(1, E / siblings); % normalize overcommit
55 unclaimed = max(0, E - siblings);
|
| /tools/testing/selftests/drivers/net/hw/ |
| A D | ethtool_mm.sh | 261 fp P E E E \
275 fp P E E E \
|
| /tools/testing/kunit/ |
| A D | mypy.ini | 4 # E.g. we can't write subprocess.Popen[str] until Python 3.9+.
|
| /tools/testing/selftests/net/packetdrill/ |
| A D | tcp_ecn_ecn-uses-ect0.pkt | 11 // ECN handshake: send EW flags in SYN packet, E flag in SYN-ACK response
|
| /tools/testing/selftests/drivers/net/mlxsw/ |
| A D | devlink_trap_control.sh | 222 $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
230 "igmp_v1_report" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
238 "igmp_v2_report" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
246 "igmp_v3_report" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:01 \
254 "igmp_v2_leave" $MZ $h1 -c 1 -a own -b 01:00:5E:00:00:02 \
|
| /tools/perf/util/ |
| A D | mem-events.c | 23 #define E(t, n, s, l, a) { .tag = t, .name = n, .event_name = s, .ldlat = l, .aux_event = a } macro
26 E("ldlat-loads", "%s/mem-loads,ldlat=%u/P", "mem-loads", true, 0),
27 E("ldlat-stores", "%s/mem-stores/P", "mem-stores", false, 0),
28 E(NULL, NULL, NULL, false, 0),
30 #undef E
|
| /tools/perf/Documentation/ |
| A D | perf.data-directory-format.txt | 52 Using CPUID GenuineIntel-6-8E-A
|
| A D | perf-lock.txt | 104 -E::
172 -E::
|
| A D | perf-top.txt | 50 -E <entries>::
341 E.g.:
406 [E]::
|
| A D | perf-mem.txt | 159 sample period, perf-mem overhead is calculated using sample weight. E.g.
|
| A D | perf-script.txt | 291 PERF_RECORD_MISC_COMM_EXEC E
|
| /tools/perf/tests/ |
| A D | make | 32 …cores := $(shell (getconf _NPROCESSORS_ONLN || grep -E -c '^processor|^CPU[0-9]' /proc/cpuinfo) 2>…
189 old_libbpf := $(shell echo '\#include <bpf/libbpf.h>' | $(CC) -E -dM -x c -| grep -q -E "define[[:s…
|
| /tools/include/uapi/ |
| A D | README | 16 E.g.:
|
| /tools/perf/pmu-events/ |
| A D | README | 131 CPUID == 'GenuineIntel-6-2E' (on x86).
|
| /tools/arch/x86/kcpuid/ |
| A D | cpuid.csv | 410 …0x12, 0, eax, 5, enclv_leaves , ENCLV leaves (E{INC,DEC}VIRTCHILD, ESE…
1059 0x80000026, 3:0, eax, 30, domain_has_hybrid_cores, This domain level has hybrid (E, …
|