Searched refs:Instruction (Results 1 – 15 of 15) sorted by relevance
| /tools/perf/scripts/python/ |
| A D | libxed.py | 80 def Instruction(self): member in LibXED
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| A D | intel-pt-events.py | 260 inst = glb_disassembler.Instruction()
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| A D | exported-sql-viewer.py | 2956 inst = self.glb.disassembler.Instruction()
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| /tools/perf/Documentation/ |
| A D | perf-amd-ibs.txt | 6 perf-amd-ibs - Support for AMD Instruction-Based Sampling (IBS) with perf tool
17 Instruction-Based Sampling (IBS) provides precise Instruction Pointer (IP)
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| A D | perf-inject.txt | 66 Decode Instruction Tracing data, replacing it with synthesized events.
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| A D | perf-script.txt | 202 The flags field is synthesized and may have a value when Instruction
218 Instruction Trace decoding. For calls and returns, it will display the
226 Instruction Trace decoding.
229 Instruction Trace decoding.
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| A D | perf-list.txt | 97 Core Complex (CCX) -> Processor x86 Core -> Instruction Based Sampling (IBS)
101 Manual Volume 2: System Programming, 13.3 Instruction-Based
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| A D | topdown.txt | 335 Please refer to Section 8.4.1 of "Intel® Architecture Instruction Set Extensions
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| A D | perf-report.txt | 131 - ins_lat: Instruction latency in core cycles. This is the global instruction
170 sampled IPC in this function. IPC means Instruction Per Cycle. If it's low,
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| /tools/perf/util/intel-pt-decoder/ |
| A D | intel-pt-insn-decoder.c | 21 #error Instruction buffer size too small
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| /tools/memory-model/Documentation/ |
| A D | references.txt | 48 For Programmers, Volume II-A: The MIPS64(R) Instruction,
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| A D | explanation.txt | 719 encoded in Itanium's Very-Long-Instruction-Word format, and it is yet
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| /tools/perf/util/ |
| A D | parse-events.l | 259 …1-icache|l1-i|l1i|L1-instruction|LLC|L2|dTLB|d-tlb|Data-TLB|iTLB|i-tlb|Instruction-TLB|branch|bran…
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| /tools/memory-model/ |
| A D | linux-kernel.cat | 86 (* Instruction execution ordering *)
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| /tools/arch/x86/kcpuid/ |
| A D | cpuid.csv | 78 0x1, 0, edx, 15, cmov , Conditional Move Instruction
316 … 0xa, 0, ebx, 1, no_insn_retired_evt , Instruction retired event not available
655 0x80000001, 0, ecx, 10, ibs , Instruction based sampling
686 0x80000001, 0, edx, 15, cmov , Conditional Move Instruction
796 0x80000008, 0, ebx, 1, irperf , Instruction retired counter MSR
878 # AMD IBS (Instruction-Based Sampling) enumeration
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