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Searched refs:cycle (Results 1 – 17 of 17) sorted by relevance

/tools/power/cpupower/bench/
A Dbenchmark.c80 unsigned int _round, cycle; in start_benchmark() local
125 for (cycle = 0; cycle < config->cycles; cycle++) { in start_benchmark()
151 for (cycle = 0; cycle < config->cycles; cycle++) { in start_benchmark()
/tools/perf/pmu-events/arch/riscv/sifive/p650/
A Dcycle-and-instruction-count.json1 ../bullet-07/cycle-and-instruction-count.json
/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/
A Dcycle-and-instruction-count.json1 ../bullet-07/cycle-and-instruction-count.json
/tools/testing/ktest/examples/include/
A Ddefaults.conf71 POWER_CYCLE = ${SCRIPTS_DIR}/${BOX}-cycle
/tools/testing/ktest/examples/
A Dcrosstests.conf216 POWER_CYCLE = cycle
/tools/testing/selftests/net/forwarding/
A Dtsn_lib.sh240 --cycle-time ${cycle_time} \
/tools/memory-model/Documentation/
A Dglossary.txt72 extended to additional CPUs, and the result is called a "cycle".
73 In a cycle, each CPU's ordering interacts with that of the next:
82 to complete the cycle. Because of the smp_mb() calls between
A Dexplanation.txt265 The counterpart to ordering is a cycle. Ordering rules out cycles:
269 involved just such an impossible cycle:
279 if those accesses would form a cycle, then the memory model predicts
1373 would generate a cycle in the hb relation: The fence would create a ppo
1504 cycle in pb, which is not possible since an instruction cannot execute
1701 Guarantee by requiring that the rb relation does not contain a cycle.
1748 a forbidden cycle. Thus the "rcu" axiom rules out this violation of
1786 forbidden cycle, violating the "rcu" axiom. Hence the outcome is not
1824 L2 ->rcu-link U0. However this cycle is not forbidden, because the
2654 various relation must not contain a cycle) doesn't apply to plain
/tools/perf/Documentation/
A Dperf-dlfilter.txt97 __u64 insn_cnt; /* For instructions-per-cycle (IPC) */
98 __u64 cyc_cnt; /* For instructions-per-cycle (IPC) */
A Dperf-intel-pt.txt151 There are two ways that instructions-per-cycle (IPC) can be calculated depending
155 and cycle events are calculated using the cycle count from CYC packets, otherwise
159 Because Intel PT does not update the cycle count on every branch or instruction,
162 the average IPC cycle count since the last IPC for that event type.
175 provide higher granularity cycle information.
178 instruction. If the cycle count is associated with an asynchronous branch
181 that instruction has retired when the cycle count is updated.
319 which selects cycle accurate mode. Each config term can have a value which
1210 option can be useful to provide higher granularity cycle information:
A Dsecurity.txt202 175,746,713 instructions # 0.67 insn per cycle
A Dperf-stat.txt94 28,982 instructions # 0.34 insn per cycle
359 for metrics like instructions per cycle can be lower - as both metrics
588 313,163,853,778 instructions:u # 1.36 insn per cycle
A Dperf-script-python.txt654 insn_cnt - instruction count for determining instructions-per-cycle (IPC)
655 cyc_cnt - cycle count for determining IPC
A Dperf-script.txt228 The ipc (instructions per cycle) field is synthesized and may have a value when
/tools/memory-model/litmus-tests/
A DREADME171 scheme covers litmus tests having a single cycle that passes through
255 within the cycle through a given litmus test can be provided by the herd7
/tools/bpf/bpftool/Documentation/
A Dbpftool-prog.rst352 42518139 instructions # 1.06 insns per cycle (83.39%)
/tools/arch/x86/kcpuid/
A Dcpuid.csv159 … 0x6, 0, eax, 5, ecmd , Clock modulation duty cycle extension
315 0xa, 0, ebx, 0, no_core_cycle_evt , Core cycle event not available
450 …0x14, 0, ebx, 1, psb_cyc , Configurable PSB and cycle-accurate mo…

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