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Searched refs:intid (Results 1 – 13 of 13) sorted by relevance

/tools/testing/selftests/kvm/include/arm64/
A Dgic.h35 #define INTID_IS_SGI(intid) (0 <= (intid) && (intid) < MIN_PPI) argument
36 #define INTID_IS_PPI(intid) (MIN_PPI <= (intid) && (intid) < MIN_SPI) argument
37 #define INTID_IS_SPI(intid) (MIN_SPI <= (intid) && (intid) <= MAX_SPI) argument
40 void gic_irq_enable(unsigned int intid);
41 void gic_irq_disable(unsigned int intid);
43 void gic_set_eoi(unsigned int intid);
44 void gic_set_dir(unsigned int intid);
53 void gic_irq_set_active(unsigned int intid);
55 bool gic_irq_get_active(unsigned int intid);
56 void gic_irq_set_pending(unsigned int intid);
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A Dvgic.h23 void kvm_irq_set_level_info(int gic_fd, uint32_t intid, int level);
24 int _kvm_irq_set_level_info(int gic_fd, uint32_t intid, int level);
26 void kvm_arm_irq_line(struct kvm_vm *vm, uint32_t intid, int level);
27 int _kvm_arm_irq_line(struct kvm_vm *vm, uint32_t intid, int level);
30 void kvm_irq_write_ispendr(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu);
31 void kvm_irq_write_isactiver(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu);
A Dgic_v3_its.h16 u32 collection_id, u32 intid);
/tools/testing/selftests/kvm/lib/arm64/
A Dgic.c62 void gic_irq_enable(unsigned int intid) in gic_irq_enable() argument
65 gic_common_ops->gic_irq_enable(intid); in gic_irq_enable()
68 void gic_irq_disable(unsigned int intid) in gic_irq_disable() argument
71 gic_common_ops->gic_irq_disable(intid); in gic_irq_disable()
77 unsigned int intid; in gic_get_and_ack_irq() local
82 intid = irqstat & GENMASK(23, 0); in gic_get_and_ack_irq()
84 return intid; in gic_get_and_ack_irq()
87 void gic_set_eoi(unsigned int intid) in gic_set_eoi() argument
90 gic_common_ops->gic_write_eoir(intid); in gic_set_eoi()
93 void gic_set_dir(unsigned int intid) in gic_set_dir() argument
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A Dgic_private.h13 void (*gic_irq_enable)(unsigned int intid);
14 void (*gic_irq_disable)(unsigned int intid);
20 void (*gic_set_priority)(uint32_t intid, uint32_t prio);
21 void (*gic_irq_set_active)(uint32_t intid);
22 void (*gic_irq_clear_active)(uint32_t intid);
23 bool (*gic_irq_get_active)(uint32_t intid);
24 void (*gic_irq_set_pending)(uint32_t intid);
25 void (*gic_irq_clear_pending)(uint32_t intid);
26 bool (*gic_irq_get_pending)(uint32_t intid);
27 void (*gic_irq_set_config)(uint32_t intid, bool is_edge);
A Dvgic.c85 uint64_t attr = 32 * (intid / 32); in _kvm_irq_set_level_info()
86 uint64_t index = intid % 32; in _kvm_irq_set_level_info()
103 int ret = _kvm_irq_set_level_info(gic_fd, intid, level); in kvm_irq_set_level_info()
110 uint32_t irq = intid & KVM_ARM_IRQ_NUM_MASK; in _kvm_arm_irq_line()
115 if (INTID_IS_PPI(intid)) in _kvm_arm_irq_line()
125 int ret = _kvm_arm_irq_line(vm, intid, level); in kvm_arm_irq_line()
133 uint64_t reg = intid / 32; in vgic_poke_irq()
134 uint64_t index = intid % 32; in vgic_poke_irq()
137 bool intid_is_private = INTID_IS_SGI(intid) || INTID_IS_PPI(intid); in vgic_poke_irq()
164 vgic_poke_irq(gic_fd, intid, vcpu, GICD_ISPENDR); in kvm_irq_write_ispendr()
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A Dgic_v3.c79 switch (intid) { in get_intid_range()
186 index = intid % fields_per_reg; in gicv3_access_reg()
203 gicv3_access_reg(intid, offset, reg_bits, in gicv3_write_reg()
212 gicv3_access_reg(intid, offset, reg_bits, in gicv3_read_reg()
230 gicv3_write_reg(intid, GICD_ICFGR, 32, 2, val); in gicv3_irq_set_config()
233 static void gicv3_irq_enable(uint32_t intid) in gicv3_irq_enable() argument
242 static void gicv3_irq_disable(uint32_t intid) in gicv3_irq_disable() argument
251 static void gicv3_irq_set_active(uint32_t intid) in gicv3_irq_set_active() argument
261 static bool gicv3_irq_get_active(uint32_t intid) in gicv3_irq_get_active() argument
268 gicv3_write_reg(intid, GICD_ISPENDR, 32, 1, 1); in gicv3_irq_set_pending()
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A Dgic_v3_its.c227 u32 collection_id, u32 intid) in its_send_mapti_cmd() argument
234 its_encode_phys_id(&cmd, intid); in its_send_mapti_cmd()
/tools/testing/selftests/kvm/arm64/
A Dvgic_irq.c182 gic_set_eoi(intid); in guest_irq_generic_handler()
346 uint32_t intid; in wait_for_and_activate_irq() local
353 return intid; in wait_for_and_activate_irq()
563 for (i = intid; i < (uint64_t)intid + num; i++) in kvm_set_gsi_routing_irqchip_check()
611 if (INTID_IS_SGI(intid) || INTID_IS_PPI(intid)) in kvm_routing_and_irqfd_check()
623 for (f = 0, i = intid; i < (uint64_t)intid + num; i++, f++) in kvm_routing_and_irqfd_check()
626 for (f = 0, i = intid; i < (uint64_t)intid + num; i++, f++) { in kvm_routing_and_irqfd_check()
631 for (f = 0, i = intid; i < (uint64_t)intid + num; i++, f++) { in kvm_routing_and_irqfd_check()
638 for (f = 0, i = intid; i < (uint64_t)intid + num; i++, f++) in kvm_routing_and_irqfd_check()
694 for (i = intid; i < intid + num; i++) in run_guest_cmd()
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A Darch_timer.c55 static void guest_validate_irq(unsigned int intid, in guest_validate_irq() argument
64 if (intid == IAR_SPURIOUS) in guest_validate_irq()
94 GUEST_ASSERT_EQ(intid, timer_irq); in guest_validate_irq()
107 unsigned int intid = gic_get_and_ack_irq(); in guest_irq_handler() local
111 guest_validate_irq(intid, shared_data); in guest_irq_handler()
113 gic_set_eoi(intid); in guest_irq_handler()
A Dvgic_lpi_stress.c54 u32 intid = gic_get_and_ack_irq(); in guest_irq_handler() local
56 if (intid == IAR_SPURIOUS) in guest_irq_handler()
59 GUEST_ASSERT(intid >= GIC_LPI_OFFSET); in guest_irq_handler()
60 gic_set_eoi(intid); in guest_irq_handler()
65 u32 coll_id, device_id, event_id, intid = GIC_LPI_OFFSET; in guest_setup_its_mappings() local
83 event_id, coll_id, intid++); in guest_setup_its_mappings()
A Darch_timer_edge_cases.c147 unsigned int intid = gic_get_and_ack_irq(); in guest_irq_handler() local
153 if (intid == IAR_SPURIOUS) { in guest_irq_handler()
158 if (intid == ptimer_irq) in guest_irq_handler()
160 else if (intid == vtimer_irq) in guest_irq_handler()
178 gic_set_eoi(intid); in guest_irq_handler()
/tools/testing/selftests/kvm/riscv/
A Darch_timer.c21 unsigned int intid = regs->cause & ~CAUSE_IRQ_FLAG; in guest_irq_handler() local
32 GUEST_ASSERT_EQ(intid, timer_irq); in guest_irq_handler()

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