Searched refs:miss (Results 1 – 12 of 12) sorted by relevance
| /tools/testing/selftests/mm/ |
| A D | vm_util.h | 90 bool miss, bool wp, bool minor);
93 bool miss, bool wp, bool minor, uint64_t *ioctls);
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| A D | uffd-unit-tests.c | 1459 do_register_ioctls_test(uffd_test_args_t *args, bool miss, bool wp, bool minor) in do_register_ioctls_test() argument
1466 miss, wp, minor, &ioctls); in do_register_ioctls_test()
1476 (!miss && !wp && !minor)) { in do_register_ioctls_test()
1479 "with wrong errno=%d", miss, wp, minor, ret); in do_register_ioctls_test()
1484 if (miss) in do_register_ioctls_test()
1494 "returned=0x%"PRIx64, miss, wp, minor, expected, ioctls); in do_register_ioctls_test()
1502 int miss, wp, minor; in uffd_register_ioctls_test() local
1504 for (miss = 0; miss <= 1; miss++) in uffd_register_ioctls_test()
1507 do_register_ioctls_test(args, miss, wp, minor); in uffd_register_ioctls_test()
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| A D | vm_util.c | 343 bool miss, bool wp, bool minor, uint64_t *ioctls) in uffd_register_with_ioctls() argument
349 if (miss) in uffd_register_with_ioctls()
369 bool miss, bool wp, bool minor) in uffd_register() argument
372 miss, wp, minor, NULL); in uffd_register()
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| /tools/perf/Documentation/ |
| A D | perf-amd-ibs.txt | 21 hit/miss, d-TLB hit/miss, cache miss latency, load/store data source, branch
23 with details like i-cache hit/miss, i-TLB hit/miss, fetch latency etc. IBS is
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| A D | perf-arm-spe.txt | 19 in cycles. For loads and stores it also includes data address, cache miss events, and data origin.
80 - Allows correlation between an instruction and events, such as TLB and cache miss. (Data source
185 21 l1d-miss
187 5 llc-miss
189 2 tlb-miss
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| A D | perf-record.txt | 216 na, none, hit, miss, hitm, fwd, peer (for mem_snoop)
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| /tools/perf/util/ |
| A D | bpf-filter.l | 147 miss { return constant(PERF_MEM_SNOOP_MISS); }
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| A D | mem-events.c | 334 u64 hit, miss; in perf_mem__tlb_scnprintf() local
343 miss = m & PERF_MEM_TLB_MISS; in perf_mem__tlb_scnprintf()
361 if (miss) in perf_mem__tlb_scnprintf()
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| A D | parse-events.l | 260 …|write|prefetch|prefetches|speculative-read|speculative-load|refs|Reference|ops|access|misses|miss)
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| /tools/testing/selftests/net/openvswitch/ |
| A D | ovs-dpctl.py | 1874 up.miss(msg)
2452 def miss(self, packetmsg): member in OvsFlow
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| /tools/arch/x86/kcpuid/ |
| A D | cpuid.csv | 891 0x8000001b, 0, eax, 11, ibs_l3_miss_filter , IBS L3-miss filtering supported (…
911 0x8000001c, 0, ecx, 5, lwp_data_adddr , Cache miss events report the data…
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| /tools/memory-model/Documentation/ |
| A D | litmus-tests.txt | 950 reordering compilers and CPUs can carry out, leading it to miss
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