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Searched refs:timing (Results 1 – 10 of 10) sorted by relevance

/tools/testing/selftests/seccomp/
A Dseccomp_benchmark.c25 unsigned long long timing(clockid_t clk_id, unsigned long long samples) in timing() function
217 native = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; in main()
227 bitmap1 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; in main()
234 bitmap2 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; in main()
241 filter1 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; in main()
248 filter2 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; in main()
/tools/testing/selftests/lkdtm/
A Dtests.txt67 #REFCOUNT_TIMING timing only
68 #ATOMIC_TIMING timing only
/tools/power/pm-graph/config/
A Dcgskip.txt15 # low level scheduling and timing
/tools/verification/rv/
A DREADME.txt9 analysing the logical and timing behavior of Linux.
/tools/perf/Documentation/
A Dintel-bts.txt9 notable difference is that Intel BTS has no timing information and as a
A Dperf-intel-pt.txt94 Also note that the coarseness of Intel PT timing information will start to
157 the values are less accurate because the timing is less accurate.
339 timing information. In some cases it is possible to decode
340 without timing information, for example a per-thread context
393 also affect the granularity to timing information in the absence
397 Produces MTC timing packets.
443 Produces CYC timing packets.
942 That is because, in the absence of timing information, the sched_switch events
1045 Emitting a PSB+ can cause a CPU a slight delay. When doing timing analysis
1046 of code with Intel PT, it is useful to know if a timing bubble was caused
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/tools/lib/perf/Documentation/
A Dlibperf-counting.txt93 The `read_format` setup tells perf to include timing details together with each count.
/tools/power/pm-graph/
A DREADME8 pm-graph: suspend/resume/boot timing analysis tools
630 Suspend/Resume timing test initiated
/tools/arch/x86/kcpuid/
A Dcpuid.csv452 …0x14, 0, ebx, 3, mtc_timing , MTC timing packet; COFI-based packets …
/tools/memory-model/Documentation/
A Dexplanation.txt186 timing. In other words, the instructions from the various CPUs get
1827 The following instruction timing diagram shows how it might actually

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