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/drivers/clk/sunxi-ng/
A Dccu_div.h106 _table, _flags) \ argument
132 _gate, _flags) \ argument
151 _gate, _flags) \ argument
168 _gate, _flags) \ argument
178 _gate, _flags) \ argument
187 _flags) \ argument
197 _flags) \ argument
211 _flags) \ argument
235 _flags) \ argument
259 _flags) \ argument
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A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
72 _gate, _prediv, _flags) \ argument
86 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ argument
100 _gate, _prediv, _flags) \ argument
A Dccu_mp.h38 _gate, _postdiv, _flags) \ argument
60 _gate, _postdiv, _flags)\ argument
81 _gate, _flags) \ argument
100 _flags) \ argument
112 _flags) \ argument
134 _gate, _flags, _features) \ argument
154 _gate, _flags) \ argument
165 _gate, _flags) \ argument
177 _flags) \ argument
188 _gate, _flags) \ argument
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A Dccu_mux.h51 _flags, _features) \ argument
67 _width, _gate, _flags) \ argument
75 _flags) \ argument
81 _shift, _width, _gate, _flags) \ argument
87 _flags) \ argument
92 _shift, _width, _gate, _flags) \ argument
106 _shift, _width, _flags) \ argument
111 _shift, _width, _gate, _flags) \ argument
A Dccu_nm.h43 _gate, _lock, _flags) \ argument
66 _gate, _lock, _flags) \ argument
91 _gate, _lock, _flags) \ argument
119 _gate, _lock, _flags, \ argument
149 _gate, _lock, _flags) \ argument
169 _gate, _lock, _flags) \ argument
185 _gate, _lock, _flags) \ argument
/drivers/clk/sprd/
A Dgate.h32 _sc_offset, _enable_mask, _flags, \ argument
48 _sc_offset, _enable_mask, _flags, \ argument
61 _enable_mask, _flags, _gate_flags) \ argument
67 _enable_mask, _flags, _gate_flags) \ argument
83 _flags, _gate_flags, \ argument
91 _sc_offset, _enable_mask, _flags, \ argument
98 _sc_offset, _enable_mask, _flags, \ argument
105 _enable_mask, _flags, _gate_flags) \ argument
111 _sc_offset, _enable_mask, _flags, \ argument
120 _enable_mask, _flags, \ argument
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A Dcomposite.h23 _dwidth, _flags, _fn) \ argument
36 _mshift, _mwidth, _dshift, _dwidth, _flags) \ argument
42 _mwidth, _dshift, _dwidth, _flags) \ argument
48 _dwidth, _flags) \ argument
55 _mwidth, _dshift, _dwidth, _flags) \ argument
63 _flags) \ argument
71 _dwidth, _flags) \ argument
A Dmux.h40 _reg, _shift, _width, _flags, _fn) \ argument
52 _reg, _shift, _width, _flags) \ argument
58 _shift, _width, _flags) \ argument
63 _reg, _shift, _width, _flags) \ argument
69 _shift, _width, _flags) \ argument
A Ddiv.h41 _shift, _width, _flags, _fn) \ argument
53 _shift, _width, _flags) \ argument
58 _shift, _width, _flags) \ argument
63 _shift, _width, _flags) \ argument
/drivers/clk/spacemit/
A Dccu_mix.h55 #define CCU_MIX_INITHW(_name, _parent, _ops, _flags) \ argument
65 #define CCU_MIX_INITHW_PARENTS(_name, _parents, _ops, _flags) \ argument
68 #define CCU_GATE_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _flags) \ argument
105 _mul, _flags) \ argument
121 _mask_gate, _flags) \ argument
133 _mask_gate, _flags) \ argument
145 _muxshift, _muxwidth, _mask_gate, _flags) \ argument
159 _muxwidth, _mask_gate, _flags) \ argument
175 _flags) \ argument
181 _mask_fc, _muxshift, _muxwidth, _flags) \ argument
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A Dccu_ddn.h23 #define CCU_DDN_INIT(_name, _parent, _flags) \ argument
27 _den_shift, _den_width, _flags) \ argument
/drivers/clk/sophgo/
A Dclk-cv18xx-ip.h79 _div_flag, _ops, _flags) \ argument
94 _fix_div, _ops, _flags) \ argument
107 _div_flag, _flags) \ argument
115 _div_flag, _bypass_reg, _bypass_shift, _flags)\ argument
127 _fix_div, _flags) \ argument
136 _flags) \ argument
150 _ops, _flags) \ argument
166 _mux_reg, _mux_shift, _mux_width, _flags) \ argument
177 _bypass_reg, _bypass_shift, _flags) \ argument
198 _parent2sel, _sel2parent0, _sel2parent1, _flags) \ argument
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A Dclk-sg2044.c288 #define SG2044_CLK_COMMON_PDATA(_id, _name, _parents, _op, _flags) \ argument
295 #define SG2044_CLK_COMMON_PHWS(_id, _name, _parents, _op, _flags) \ argument
302 #define DEFINE_SG2044_GATEABLE_DIV(_id, _name, _parent, _flags, \ argument
318 #define DEFINE_SG2044_DIV(_id, _name, _parent, _flags, \ argument
334 #define DEFINE_SG2044_DIV_PDATA(_id, _name, _parent, _flags, \ argument
350 #define DEFINE_SG2044_DIV_RO(_id, _name, _parent, _flags, \ argument
366 #define DEFINE_SG2044_MUX(_id, _name, _parent, _flags, \ argument
380 #define DEFINE_SG2044_GATE(_id, _name, _parent, _flags, \ argument
/drivers/clk/actions/
A Dowl-composite.h38 _mux, _gate, _div, _flags) \ argument
53 _gate, _div, _flags) \ argument
67 _mux, _gate, _factor, _flags) \ argument
82 _gate, _mul, _div, _flags) \ argument
98 _mux, _gate, _flags) \ argument
A Dowl-pll.h56 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
71 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
86 _flags) \ argument
A Dowl-gate.h35 _bit_idx, _gate_flags, _flags) \ argument
48 _bit_idx, _gate_flags, _flags) \ argument
/drivers/clk/starfive/
A Dclk-starfive-jh71x0.h32 #define JH71X0_GATE(_idx, _name, _flags, _parent) \ argument
48 #define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \ argument
64 #define JH71X0__MUX(_idx, _name, _flags, _nparents, ...) \ argument
72 #define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) \ argument
89 #define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) \ argument
/drivers/clk/mediatek/
A Dclk-mt7988-infracfg.c128 #define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
132 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
136 #define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
140 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
A Dclk-mux.h44 _upd, _flags, _ops) { \ argument
64 _gate, _upd_ofs, _upd, _flags, _ops) \ argument
72 _width, _gate, _upd_ofs, _upd, _flags, _ops) \ argument
83 _gate, _upd_ofs, _upd, _flags) \ argument
91 _shift, _width, _gate, _upd_ofs, _upd, _flags) \ argument
A Dclk-mt8183-apmixedsys.c24 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
54 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
81 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
A Dclk-mt6797.c430 #define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
437 #define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
599 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
619 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
A Dclk-mt7981-apmixed.c25 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
38 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
/drivers/gpu/drm/amd/pm/inc/
A Damdgpu_pm.h101 #define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _flags, ...) \ argument
107 #define AMDGPU_DEVICE_ATTR(_name, _mode, _flags, ...) \ argument
112 #define AMDGPU_DEVICE_ATTR_RW(_name, _flags, ...) \ argument
116 #define AMDGPU_DEVICE_ATTR_RO(_name, _flags, ...) \ argument
/drivers/net/wireless/st/cw1200/
A Dmain.c60 #define RATETAB_ENT(_rate, _rateid, _flags) \ argument
101 #define CHAN2G(_channel, _freq, _flags) { \ argument
110 #define CHAN5G(_channel, _flags) { \ argument
/drivers/clk/stm32/
A Dclk-stm32mp1.c1184 #define FIXED_FACTOR(_id, _name, _parent, _flags, _mult, _div)\ argument
1197 #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\ argument
1234 #define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\ argument
1266 #define STM32_GATE(_id, _name, _parent, _flags, _gate)\ argument
1276 #define STM32_GATE_PDATA(_id, _name, _parent, _flags, _gate)\ argument
1315 #define MGATE_MP1(_id, _name, _parent, _flags, _mgate)\ argument
1319 #define MGATE_MP1_PDATA(_id, _name, _parent, _flags, _mgate)\ argument
1368 #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\ argument
1383 #define PCLK(_id, _name, _parent, _flags, _mgate)\ argument
1386 #define PCLK_PDATA(_id, _name, _parent, _flags, _mgate)\ argument
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