Home
last modified time | relevance | path

Searched refs:CPU (Results 1 – 25 of 254) sorted by relevance

1234567891011

/arch/sparc/kernel/
A Dcpu.c72 CPU(-1, NULL)
96 CPU(-1, NULL)
111 CPU(-1, NULL)
120 CPU(-1, NULL)
135 CPU(-1, NULL)
148 CPU(-1, NULL)
158 CPU(-1, NULL)
167 CPU(-1, NULL)
176 CPU(-1, NULL)
189 CPU(-1, NULL)
[all …]
/arch/mips/bcm63xx/
A DKconfig2 menu "CPU support"
6 bool "support 3368 CPU"
11 bool "support 6328 CPU"
16 bool "support 6338 CPU"
21 bool "support 6345 CPU"
25 bool "support 6348 CPU"
30 bool "support 6358 CPU"
35 bool "support 6362 CPU"
40 bool "support 6368 CPU"
/arch/arm64/boot/dts/marvell/
A Dac5x-rd-carrier-cn9131.dts6 * Utilizing the CN913x COM Express CPU module board.
8 * only maintains a PCIe link with the CPU module,
13 * which would allow it to use an external CN9131 CPU COM Express module,
19 * When the board boots in the external CPU mode, the internal CPU is disabled,
21 * is no need to describe this internal (disabled CPU) in the device tree.
23 * There is no CPU booting in this mode on the carrier, only on the
24 * CN9131 COM Express CPU module.
25 * What runs the Linux is the CN9131 on the COM Express CPU module,
34 model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module";
A Dac5x-rd-carrier.dtsi7 * a PCIe link with the COM Express CPU module, which does not
11 * box using the internal CPU, or you can move the switch on the back of
13 * which would allow it to use an external CPU COM Express module,
22 * When the board boots in the external CPU mode, the internal CPU is disabled,
24 * is no need to describe this internal (disabled CPU) in the device tree.
26 * There is no CPU booting in this mode on the carrier,
27 * only on the COM Express CPU module.
/arch/arc/plat-axs10x/
A DKconfig21 typically contain a CPU and memory.
27 bool "AXS101 with AXC001 CPU Card (ARC 770D/EM6/AS221)"
29 This adds support for the 770D/EM6/AS221 CPU Card. Only the ARC
37 bool "AXS103 with AXC003 CPU Card (ARC HS38x)"
40 This adds support for the HS38x CPU Card.
/arch/powerpc/crypto/
A DKconfig3 menu "Accelerated Cryptographic Algorithms for CPU (powerpc)"
39 - CPU selection: e500 (8540)
49 tristate "Stitched AES/GCM acceleration support on P10 or later CPU (PPC)"
64 later CPU. This module supports stitched acceleration for AES/GCM.
73 tristate "Encryption acceleration support on P8 CPU"
82 Support for VMX cryptographic acceleration instructions on Power8 CPU.
/arch/x86/
A DKconfig.cpu2 # Put here option for CPU selection and depending optimization
221 incarnations of the CPU.
259 bool "Build and optimize for local/native CPU"
374 CPU might render the kernel unbootable.
388 CPU might render the kernel unbootable.
401 CPU might render the kernel unbootable.
415 CPU might render the kernel unbootable.
428 CPU might render the kernel unbootable.
442 CPU might render the kernel unbootable.
456 CPU might render the kernel unbootable.
[all …]
/arch/arm/common/
A Dmcpm_head.S58 mla r4, r3, r10, r9 @ r4 = canonical CPU index
90 @ Signal that this CPU is coming UP:
97 @ state, because there is at least one active CPU (this CPU).
125 @ Any CPU trying to take the cluster into CLUSTER_GOING_DOWN from this
178 @ If a platform-specific CPU setup hook is needed, it is
182 mov r0, #0 @ first (CPU) affinity level
186 @ Mark the CPU as up:
194 ldr r5, [r6, r4, lsl #2] @ r5 = CPU entry vector
/arch/csky/
A DKconfig134 For SMP, CPU needs "ldex&stex" instructions for atomic operations.
191 prompt "CPU MODEL"
195 bool "CSKY CPU ck610"
201 bool "CSKY CPU ck810"
206 bool "CSKY CPU ck807"
210 bool "CSKY CPU ck860"
298 bool "CPU has VDSP coprocessor"
302 bool "CPU has FPU coprocessor"
306 bool "CPU has Icache invalidate instructions"
310 bool "CPU has Trusted Execution Environment"
[all …]
/arch/arm/boot/dts/aspeed/
A Daspeed-bmc-tyan-s7106.dts180 /* CPU fan #0 */
186 /* CPU fan #1 */
260 * - CPU #0 memory error LED @ 0x3A
261 * - CPU #1 memory error LED @ 0x3C
328 * - CPU #0 channels ABC VDDQ @ 0x80
332 * - CPU #0 VCCIO & VMCP @ 0x52
333 * - CPU #1 VCCIO & VMCP @ 0x53
334 * - CPU #0 VCCIN @ 0xC0
335 * - CPU #0 VSA @ 0xC2
336 * - CPU #1 VCCIN @ 0xC4
[all …]
/arch/arm64/boot/dts/renesas/
A Dr8a779g0-white-hawk-cpu.dts3 * Device Tree Source for the standalone R-Car V4H White Hawk CPU board
12 model = "Renesas White Hawk CPU board based on r8a779g0";
A Dr8a779g0-white-hawk-cpu.dtsi3 * Device Tree Source for the R-Car V4H White Hawk CPU board
12 model = "Renesas White Hawk CPU board";
A Dr8a779g0-white-hawk.dts3 * Device Tree Source for the R-Car V4H White Hawk CPU and BreakOut boards
13 model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0";
A Dr8a779f0-spider.dts3 * Device Tree Source for the Spider CPU and BreakOut boards
13 model = "Renesas Spider CPU and Breakout boards based on r8a779f0";
/arch/arm/kernel/
A Dhyp-stub.S46 cmp \mode, \reg1 @ matches primary CPU boot mode?
73 @ Call this from the primary CPU
102 retne lr @ give up if the CPU is not in HYP mode
/arch/arc/boot/dts/
A Daxc001.dtsi7 * Device tree for AXC001 770D/EM6/AS221 CPU card
8 * Note that this file only supports the 770D CPU
44 * this GPIO block ORs all interrupts on CPU card (creg,..)
84 * which acts as a wire between MB INTC and CPU INTC.
87 * CPU INTC, thus we set "interrupts = <7>" instead of
/arch/sh/
A DKconfig307 if you have a 100 Mhz SH-3 HD6417708R CPU.
320 Select SH7710 if you have a SH3-DSP SH7710 CPU.
327 Select SH7712 if you have a SH3-DSP SH7712 CPU.
337 Select SH7720 if you have a SH3-DSP SH7720 CPU.
376 or if you have a HD6417751R CPU.
397 Select SH7723 if you have an SH-MobileR2 CPU.
408 Select SH7724 if you have an SH-MobileR2R CPU.
416 Select SH7734 if you have a SH4A SH7734 CPU.
424 Select SH7757 if you have a SH4A SH7757 CPU.
534 menu "CPU Frequency scaling"
[all …]
/arch/mips/jazz/
A DKconfig7 This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
18 This is a machine with a R4000 100 MHz CPU. To compile a Linux
28 This is a machine with a R4000 100 MHz CPU. To compile a Linux
/arch/arm64/boot/dts/hisilicon/
A Dhi6220-coresight.dtsi378 /* CTI - CPU-0 */
391 /* CTI - CPU-1 */
404 /* CTI - CPU-2 */
417 /* CTI - CPU-3 */
430 /* CTI - CPU-4 */
443 /* CTI - CPU-5 */
456 /* CTI - CPU-6 */
469 /* CTI - CPU-7 */
/arch/arm/boot/dts/nxp/imx/
A Dimx6s-dhcom-drc02.dts14 * but the Solo is actually a DualLite with only one CPU. So use
15 * DualLite for the Solo and disable one CPU node.
/arch/arm/mach-tegra/
A Dreset-handler.S56 @ & ext flags for CPU power mgnt
182 and r10, r10, #0x3 @ R10 = CPU number
184 mov r11, r11, lsl r10 @ R11 = CPU mask
190 bleq __die @ CPU not present (to OS)
279 wfi @ CPU should be power gated here
/arch/m68k/
A DKconfig.cpu5 prompt "CPU/machine family support"
22 bool "Classic M68K CPU/machine family support"
27 bool "Coldfire CPU family support"
45 (3/50, 3/60, 3/1xx, 3/2xx systems). These use a classic 68020 CPU
63 The Freescale (was Motorola) 68000 CPU is the first generation of
64 the well known M68K family of processors. The CPU core as well as
65 being available as a stand alone CPU was also used in many
502 specific to the exact CPU that you are using.
524 Use all of the ColdFire CPU cache memory as a data cache.
542 The ColdFire CPU cache is set into Write-through mode.
[all …]
/arch/powerpc/boot/dts/
A Diss4xx-mpic.dts36 model = "PowerPC,4xx"; // real CPU changed in sim
50 model = "PowerPC,4xx"; // real CPU changed in sim
66 model = "PowerPC,4xx"; // real CPU changed in sim
82 model = "PowerPC,4xx"; // real CPU changed in sim
/arch/arm/mach-sa1100/
A Dsleep.S50 @ Adjust memory timing before lowering CPU clock
53 @ delay 90us and set CPU PLL to lowest speed
137 @ about 7 ns out of the entire time that the CPU is running!
/arch/arm/mach-mvebu/
A Dpmsu_ll.S15 orr r1, r1, #0x8 @ SCU CPU Power Status Register
16 mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID

Completed in 28 milliseconds

1234567891011