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Searched refs:CSR_VSTIMECMP (Results 1 – 2 of 2) sorted by relevance

/arch/riscv/kvm/
A Dvcpu_timer.c75 ncsr_write(CSR_VSTIMECMP, ncycles & 0xFFFFFFFF); in kvm_riscv_vcpu_update_vstimecmp()
78 ncsr_write(CSR_VSTIMECMP, ncycles); in kvm_riscv_vcpu_update_vstimecmp()
310 ncsr_write(CSR_VSTIMECMP, (u32)t->next_cycles); in kvm_riscv_vcpu_timer_restore()
313 ncsr_write(CSR_VSTIMECMP, t->next_cycles); in kvm_riscv_vcpu_timer_restore()
331 t->next_cycles = ncsr_read(CSR_VSTIMECMP); in kvm_riscv_vcpu_timer_sync()
334 t->next_cycles = ncsr_read(CSR_VSTIMECMP); in kvm_riscv_vcpu_timer_sync()
361 csr_write(CSR_VSTIMECMP, -1UL); in kvm_riscv_vcpu_timer_save()
/arch/riscv/include/asm/
A Dcsr.h354 #define CSR_VSTIMECMP 0x24D macro

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