Searched refs:MASK (Results 1 – 6 of 6) sorted by relevance
| /arch/x86/kernel/cpu/mce/ |
| A D | severity.c | 66 #define MASK(x, y) .mask = x, .result = y macro
115 SER, MASK(MCI_UC_AR|MCACOD_SCRUBMSK, MCI_STATUS_UC|MCACOD_SCRUB)
119 SER, MASK(MCI_UC_AR|MCACOD, MCI_STATUS_UC|MCACOD_L3WB)
130 SER, MASK(MCI_STATUS_UC|MCI_ADDR|0xffffeff0, MCI_ADDR|0x001000c0),
137 SER, MASK(MCI_UC_SAR, MCI_STATUS_UC)
142 MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR)
158 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR, MCI_UC_SAR|MCI_ADDR),
163 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
201 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_SAR)
206 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S)
[all …]
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| /arch/arm/mach-rpc/ |
| A D | irq.c | 15 #define MASK 0x08 macro
130 val = readb(base + MASK); in iomd_irq_mask_ack()
131 writeb(val & ~mask, base + MASK); in iomd_irq_mask_ack()
140 val = readb(base + MASK); in iomd_irq_mask()
141 writeb(val & ~mask, base + MASK); in iomd_irq_mask()
149 val = readb(base + MASK); in iomd_irq_unmask()
150 writeb(val | mask, base + MASK); in iomd_irq_unmask()
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| /arch/arm/crypto/ |
| A D | ghash-ce-core.S | 59 MASK .req d28
229 vmov.i8 MASK, #0xe1
230 vshl.u64 MASK, MASK, #57
298 vmov.i8 MASK, #0xe1
299 vshl.u64 MASK, MASK, #57
341 vmov.i8 MASK, #0xe1
342 vshl.u64 MASK, MASK, #57
601 vmov.i8 MASK, #0xe1
603 vshl.u64 MASK, MASK, #57
658 vmov.i8 MASK, #0xe1
[all …]
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| /arch/arm64/crypto/ |
| A D | ghash-ce-core.S | 16 MASK .req v4
159 movi MASK.16b, #0xe1
160 shl MASK.2d, MASK.2d, #57
201 pmull T2.1q, XL.1d, MASK.1d
209 pmull XL.1q, XL.1d, MASK.1d
618 movi MASK.16b, #0xe1
619 shl MASK.2d, MASK.2d, #57
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| /arch/loongarch/include/asm/ |
| A D | hw_breakpoint.h | 52 #define LOONGARCH_CSR_NAME_MASK MASK
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| /arch/loongarch/kernel/ |
| A D | hw_breakpoint.c | 84 GEN_READ_WB_REG_CASES(CSR_CFG_MASK, MASK, t, val); in read_wb_reg()
99 GEN_WRITE_WB_REG_CASES(CSR_CFG_MASK, MASK, t, val); in write_wb_reg()
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