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Searched refs:STATUS0 (Results 1 – 2 of 2) sorted by relevance

/arch/mips/loongson64/
A Dsmp.c262 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0); in ipi_status0_regs_init()
264 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0); in ipi_status0_regs_init()
266 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0); in ipi_status0_regs_init()
268 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0); in ipi_status0_regs_init()
270 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0); in ipi_status0_regs_init()
272 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0); in ipi_status0_regs_init()
274 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0); in ipi_status0_regs_init()
276 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0); in ipi_status0_regs_init()
278 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0); in ipi_status0_regs_init()
280 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0); in ipi_status0_regs_init()
[all …]
A Dsmp.h21 #define STATUS0 0x00 macro

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