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Searched refs:SW (Results 1 – 14 of 14) sorted by relevance

/arch/parisc/include/asm/
A Dfloppy.h28 #define SW fd_routine[use_virtual_dma&1] macro
40 #define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
41 #define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
42 #define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
/arch/x86/include/asm/
A Dfloppy.h30 #define SW fd_routine[use_virtual_dma & 1] macro
42 #define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
43 #define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
44 #define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
/arch/arm/boot/dts/samsung/
A Dexynos5250-arndale.dts39 label = "SW-TACT2";
46 label = "SW-TACT3";
53 label = "SW-TACT4";
60 label = "SW-TACT5";
67 label = "SW-TACT6";
74 label = "SW-TACT7";
A Dexynos5420-arndale-octa.dts51 label = "SW-TACT1";
/arch/powerpc/kernel/
A Dalign.c41 #define SW 0x20 /* byte swap */ macro
227 if (flags & SW) { in emulate_spe()
/arch/arm/boot/dts/marvell/
A Dkirkwood-topkick.dts121 * [SW] [*] [*] [*]
/arch/arm64/boot/dts/renesas/
A Ddraak.dtsi356 * CVBS and HDMI inputs through SW[49-53]
425 * CVBS and HDMI inputs through SW[49-53]
/arch/powerpc/platforms/
A DKconfig.cputype57 bool "Support for 603 SW loaded TLB"
62 processors don't have a HASH MMU and provide SW TLB loading.
/arch/arm64/boot/dts/rockchip/
A Drk3568-wolfvision-pf5.dts386 vcc0v9_cpu: SW {
/arch/arm/boot/dts/allwinner/
A Dsun8i-a83t-cubietruck-plus.dts308 * I/O is indirectly powered from DCDC1, through SW. It is rated
/arch/arm/mm/
A Dproc-v7.S553 orr r3, r3, #(1 << 10) @ set SW bit in "clear"
/arch/arm/boot/dts/nvidia/
A Dtegra30-colibri.dtsi909 /* SW: +V1.2_VDD_CORE */
A Dtegra30-apalis.dtsi1028 /* SW: +V1.2_VDD_CORE */
A Dtegra30-apalis-v1.1.dtsi1045 /* SW: +V1.2_VDD_CORE */

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