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Searched refs:__raw_writeq (Results 1 – 25 of 30) sorted by relevance

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/arch/mips/sibyte/common/
A Dsb_tbprof.c152 __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); in arm_tb()
165 __raw_writeq( in arm_tb()
199 __raw_writeq(M_SCD_TRACE_CFG_START_READ, in sbprof_tb_intr()
221 __raw_writeq(M_SCD_TRACE_CFG_RESET, in sbprof_tb_intr()
294 __raw_writeq(K_BCM1480_INT_MAP_I3, in sbprof_zbprof_start()
298 __raw_writeq(K_INT_MAP_I3, in sbprof_zbprof_start()
304 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); in sbprof_zbprof_start()
305 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); in sbprof_zbprof_start()
306 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2)); in sbprof_zbprof_start()
307 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3)); in sbprof_zbprof_start()
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/arch/mips/kernel/
A Dcevt-sb1250.c36 __raw_writeq(0, cfg); in sibyte_shutdown()
49 __raw_writeq(0, cfg); in sibyte_set_periodic()
50 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
51 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); in sibyte_set_periodic()
64 __raw_writeq(0, cfg); in sibyte_next_event()
65 __raw_writeq(delta - 1, init); in sibyte_next_event()
66 __raw_writeq(M_SCD_TIMER_ENABLE, cfg); in sibyte_next_event()
129 __raw_writeq(IMR_IP4_VAL, in sb1250_clockevent_init()
A Dcevt-bcm1480.c39 __raw_writeq(0, cfg); in sibyte_set_periodic()
40 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
41 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); in sibyte_set_periodic()
53 __raw_writeq(0, cfg); in sibyte_shutdown()
65 __raw_writeq(0, cfg); in sibyte_next_event()
66 __raw_writeq(delta - 1, init); in sibyte_next_event()
67 __raw_writeq(M_SCD_TIMER_ENABLE, cfg); in sibyte_next_event()
129 __raw_writeq(IMR_IP4_VAL, in sb1480_clockevent_init()
A Dcsrc-sb1250.c58 __raw_writeq(0, in sb1250_clocksource_init()
61 __raw_writeq(SB1250_HPT_VALUE, in sb1250_clocksource_init()
64 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, in sb1250_clocksource_init()
/arch/mips/sibyte/swarm/
A Drtc_m41t81.c88 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); in m41t81_read()
89 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE, in m41t81_read()
95 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, in m41t81_read()
103 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); in m41t81_read()
115 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); in m41t81_write()
116 __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA)); in m41t81_write()
117 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, in m41t81_write()
125 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); in m41t81_write()
130 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, in m41t81_write()
A Drtc_xicor1241.c63 __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); in xicor_read()
64 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA)); in xicor_read()
65 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, in xicor_read()
71 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, in xicor_read()
79 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); in xicor_read()
91 __raw_writeq(addr, SMB_CSR(R_SMB_CMD)); in xicor_write()
92 __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); in xicor_write()
93 __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, in xicor_write()
101 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); in xicor_write()
/arch/mips/sibyte/sb1250/
A Dirq.c155 __raw_writeq(pending, in ack_sb1250_irq()
230 __raw_writeq(IMR_IP2_VAL, in arch_init_irq()
234 __raw_writeq(IMR_IP2_VAL, in arch_init_irq()
247 __raw_writeq(IMR_IP3_VAL, in arch_init_irq()
250 __raw_writeq(IMR_IP3_VAL, in arch_init_irq()
255 __raw_writeq(0xffffffffffffffffULL, in arch_init_irq()
257 __raw_writeq(0xffffffffffffffffULL, in arch_init_irq()
262 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); in arch_init_irq()
263 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); in arch_init_irq()
A Dsmp.c58 __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); in sb1250_send_ipi_single()
/arch/mips/sibyte/bcm1480/
A Dirq.c168 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i), in ack_bcm1480_irq()
172 …__raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1… in ack_bcm1480_irq()
248 __raw_writeq(IMR_IP2_VAL, in arch_init_irq()
257 __raw_writeq(IMR_IP2_VAL, in arch_init_irq()
271 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + in arch_init_irq()
278 __raw_writeq(0xffffffffffffffffULL, in arch_init_irq()
280 __raw_writeq(0xffffffffffffffffULL, in arch_init_irq()
288 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H))); in arch_init_irq()
292 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L))); in arch_init_irq()
A Dsmp.c69 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); in bcm1480_send_ipi_single()
169 __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]); in bcm1480_mailbox_interrupt()
/arch/arm64/include/asm/
A Dio.h46 #define __raw_writeq __raw_writeq macro
47 static __always_inline void __raw_writeq(u64 val, volatile void __iomem *addr) in __raw_writeq() function
238 __raw_writeq(*from, to); in __const_memcpy_toio_aligned64()
286 #define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
/arch/riscv/include/asm/
A Dmmio.h38 #define __raw_writeq __raw_writeq macro
39 static inline void __raw_writeq(u64 val, volatile void __iomem *addr) in __raw_writeq() function
98 #define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
/arch/mips/sgi-ip27/
A Dip27-irq.c58 __raw_writeq(mask[0], hd->irq_mask[0]); in enable_hub_irq()
59 __raw_writeq(mask[1], hd->irq_mask[1]); in enable_hub_irq()
68 __raw_writeq(mask[0], hd->irq_mask[0]); in disable_hub_irq()
69 __raw_writeq(mask[1], hd->irq_mask[1]); in disable_hub_irq()
/arch/mips/include/asm/
A Dvideo.h31 __raw_writeq(b, addr); in fb_writeq()
A Dio.h374 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
502 #define __raw_writeq __raw_writeq macro
A Dmips-gic.h128 __raw_writeq(BIT(intr % 64), addr); \
147 __raw_writeq(_val, addr); \
A Dmips-cps.h57 __raw_writeq(val, addr_##unit##_##name()); \
/arch/alpha/kernel/
A Dio.c158 void __raw_writeq(u64 b, volatile void __iomem *addr) in __raw_writeq() function
170 EXPORT_SYMBOL(__raw_writeq);
229 __raw_writeq(b, addr); in writeq()
547 __raw_writeq(*(const u64 *)from, to); in memcpy_toio()
620 __raw_writeq(c, to); in _memset_c_io()
/arch/sparc/include/asm/
A Dio_64.h93 #define __raw_writeq __raw_writeq macro
94 static inline void __raw_writeq(u64 q, const volatile void __iomem *addr) in __raw_writeq() function
341 __raw_writeq(q, addr); in sbus_writeq()
/arch/alpha/include/asm/
A Dio.h265 extern void __raw_writeq(u64 b, volatile void __iomem *addr);
273 #define __raw_writeq __raw_writeq macro
505 extern inline void __raw_writeq(u64 b, volatile void __iomem *addr) in __raw_writeq() function
537 __raw_writeq(b, addr); in writeq()
/arch/s390/include/asm/
A Dio.h74 #define __raw_writeq zpci_write_u64 macro
/arch/mips/include/asm/sn/
A Daddrs.h263 #define LOCAL_HUB_S(_r, _d) __raw_writeq((_d), LOCAL_HUB_PTR(_r))
265 #define REMOTE_HUB_S(_n, _r, _d) __raw_writeq((_d), \
/arch/sh/include/asm/
A Dio.h31 #define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v)) macro
46 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c))
/arch/parisc/kernel/
A Dperf.c802 __raw_writeq(tmp64 | (*memaddr++ & 0x0013000000000000ul), in perf_write_image()
807 __raw_writeq(*memaddr++, runway + RUNWAY_DEBUG); in perf_write_image()
/arch/sh/kernel/
A Dio_trapped.c214 __raw_writeq(tmp, dst_addr); in copy_word()

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