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Searched refs:csr_write (Results 1 – 18 of 18) sorted by relevance

/arch/riscv/kvm/
A Dmain.c32 csr_write(CSR_HEDELEG, KVM_HEDELEG_DEFAULT); in kvm_arch_enable_virtualization_cpu()
33 csr_write(CSR_HIDELEG, KVM_HIDELEG_DEFAULT); in kvm_arch_enable_virtualization_cpu()
36 csr_write(CSR_HCOUNTEREN, 0x02); in kvm_arch_enable_virtualization_cpu()
38 csr_write(CSR_HVIP, 0); in kvm_arch_enable_virtualization_cpu()
55 csr_write(CSR_VSIE, 0); in kvm_arch_disable_virtualization_cpu()
56 csr_write(CSR_HVIP, 0); in kvm_arch_disable_virtualization_cpu()
57 csr_write(CSR_HEDELEG, 0); in kvm_arch_disable_virtualization_cpu()
58 csr_write(CSR_HIDELEG, 0); in kvm_arch_disable_virtualization_cpu()
A Daia.c131 csr_write(CSR_HVIPRIO1, csr->hviprio1); in kvm_riscv_vcpu_aia_load()
134 csr_write(CSR_VSIEH, csr->vsieh); in kvm_riscv_vcpu_aia_load()
135 csr_write(CSR_HVIPH, csr->hviph); in kvm_riscv_vcpu_aia_load()
541 csr_write(CSR_HVIPRIO1, 0x0); in kvm_riscv_aia_enable()
542 csr_write(CSR_HVIPRIO2, 0x0); in kvm_riscv_aia_enable()
544 csr_write(CSR_HVIPH, 0x0); in kvm_riscv_aia_enable()
545 csr_write(CSR_HIDELEGH, 0x0); in kvm_riscv_aia_enable()
546 csr_write(CSR_HVIPRIO1H, 0x0); in kvm_riscv_aia_enable()
547 csr_write(CSR_HVIPRIO2H, 0x0); in kvm_riscv_aia_enable()
621 csr_write(CSR_HGEIE, -1UL); in kvm_riscv_aia_init()
[all …]
A Daia_imsic.c65 csr_write(CSR_VSISELECT, __c); \
105 csr_write(CSR_VSISELECT, __c); \
144 csr_write(CSR_VSISELECT, __c); \
145 csr_write(CSR_VSIREG, __v); \
181 csr_write(CSR_VSISELECT, __c); \
384 csr_write(CSR_HSTATUS, new_hstatus); in imsic_vsfile_local_read()
418 csr_write(CSR_HSTATUS, old_hstatus); in imsic_vsfile_local_read()
456 csr_write(CSR_HSTATUS, new_hstatus); in imsic_vsfile_local_rw()
486 csr_write(CSR_HSTATUS, old_hstatus); in imsic_vsfile_local_rw()
533 csr_write(CSR_HSTATUS, new_hstatus); in imsic_vsfile_local_clear()
[all …]
A Dvcpu.c605 csr_write(CSR_VSSTATUS, csr->vsstatus); in kvm_arch_vcpu_load()
606 csr_write(CSR_VSIE, csr->vsie); in kvm_arch_vcpu_load()
607 csr_write(CSR_VSTVEC, csr->vstvec); in kvm_arch_vcpu_load()
608 csr_write(CSR_VSSCRATCH, csr->vsscratch); in kvm_arch_vcpu_load()
609 csr_write(CSR_VSEPC, csr->vsepc); in kvm_arch_vcpu_load()
610 csr_write(CSR_VSCAUSE, csr->vscause); in kvm_arch_vcpu_load()
611 csr_write(CSR_VSTVAL, csr->vstval); in kvm_arch_vcpu_load()
612 csr_write(CSR_HEDELEG, cfg->hedeleg); in kvm_arch_vcpu_load()
613 csr_write(CSR_HVIP, csr->hvip); in kvm_arch_vcpu_load()
614 csr_write(CSR_VSATP, csr->vsatp); in kvm_arch_vcpu_load()
[all …]
A Dvmid.c31 csr_write(CSR_HGATP, old | HGATP_VMID); in kvm_riscv_gstage_vmid_detect()
35 csr_write(CSR_HGATP, old); in kvm_riscv_gstage_vmid_detect()
A Dtlb.c107 csr_write(CSR_HGATP, hgatp); in kvm_riscv_local_hfence_vvma_asid_gva()
119 csr_write(CSR_HGATP, hgatp); in kvm_riscv_local_hfence_vvma_asid_all()
147 csr_write(CSR_HGATP, hgatp); in kvm_riscv_local_hfence_vvma_gva()
158 csr_write(CSR_HGATP, hgatp); in kvm_riscv_local_hfence_vvma_all()
A Dgstage.c320 csr_write(CSR_HGATP, HGATP_MODE_SV57X4 << HGATP_MODE_SHIFT); in kvm_riscv_gstage_mode_detect()
328 csr_write(CSR_HGATP, HGATP_MODE_SV48X4 << HGATP_MODE_SHIFT); in kvm_riscv_gstage_mode_detect()
335 csr_write(CSR_HGATP, 0); in kvm_riscv_gstage_mode_detect()
A Dvcpu_exit.c125 csr_write(CSR_STVEC, old_stvec); in kvm_riscv_vcpu_unpriv_read()
126 csr_write(CSR_HSTATUS, old_hstatus); in kvm_riscv_vcpu_unpriv_read()
A Dvcpu_timer.c361 csr_write(CSR_VSTIMECMP, -1UL); in kvm_riscv_vcpu_timer_save()
363 csr_write(CSR_VSTIMECMPH, -1UL); in kvm_riscv_vcpu_timer_save()
/arch/riscv/kernel/
A Dsuspend.c46 csr_write(CSR_SCRATCH, 0); in suspend_restore_csrs()
48 csr_write(CSR_ENVCFG, context->envcfg); in suspend_restore_csrs()
49 csr_write(CSR_TVEC, context->tvec); in suspend_restore_csrs()
50 csr_write(CSR_IE, context->ie); in suspend_restore_csrs()
54 csr_write(CSR_STIMECMP, context->stimecmp); in suspend_restore_csrs()
56 csr_write(CSR_STIMECMPH, context->stimecmph); in suspend_restore_csrs()
60 csr_write(CSR_SATP, context->satp); in suspend_restore_csrs()
A Dprocess.c129 csr_write(CSR_STATUS, (tmp & ~SR_UXL) | SR_UXL_32); in compat_mode_detect()
133 csr_write(CSR_STATUS, tmp); in compat_mode_detect()
/arch/riscv/mm/
A Dcontext.c192 csr_write(CSR_SATP, virt_to_pfn(mm->pgd) | in set_mm_asid()
203 csr_write(CSR_SATP, virt_to_pfn(mm->pgd) | satp_mode); in set_mm_noasid()
234 csr_write(CSR_SATP, asid_bits); in asids_init()
237 csr_write(CSR_SATP, old); in asids_init()
A Dkasan_init.c489 csr_write(CSR_SATP, PFN_DOWN(__pa(tmp_pg_dir)) | satp_mode); in kasan_init()
534 csr_write(CSR_SATP, PFN_DOWN(__pa(swapper_pg_dir)) | satp_mode); in kasan_init()
A Dinit.c899 csr_write(CSR_SATP, identity_satp); in set_satp_mode()
1369 csr_write(CSR_SATP, PFN_DOWN(__pa_symbol(swapper_pg_dir)) | satp_mode); in setup_vm_final()
/arch/riscv/include/asm/
A Dvector.h159 csr_write(CSR_STATUS, status); in __vstate_csr_save()
185 csr_write(CSR_VXRM, (src->vcsr >> CSR_VXRM_SHIFT) & CSR_VXRM_MASK); in __vstate_csr_restore()
186 csr_write(CSR_VXSAT, src->vcsr & CSR_VXSAT_MASK); in __vstate_csr_restore()
189 csr_write(CSR_STATUS, status); in __vstate_csr_restore()
191 csr_write(CSR_VCSR, src->vcsr); in __vstate_csr_restore()
A Dswitch_to.h81 csr_write(CSR_ENVCFG, envcfg); in envcfg_update_bits()
A Dkvm_nacl.h226 csr_write(__csr, __val); \
A Dcsr.h536 #define csr_write(csr, val) \ macro

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