| /arch/x86/kernel/cpu/ |
| A D | cacheinfo.c | 53 } split; member
62 } split; member
69 } split; member
207 eax->split.is_self_initializing = 1; in legacy_amd_cpuid4()
208 eax->split.type = types[index]; in legacy_amd_cpuid4()
209 eax->split.level = levels[index]; in legacy_amd_cpuid4()
210 eax->split.num_threads_sharing = 0; in legacy_amd_cpuid4()
214 eax->split.is_fully_associative = 1; in legacy_amd_cpuid4()
226 if (eax.split.type == CTYPE_NULL) in cpuid4_info_fill_done()
441 switch (id4.eax.split.level) { in intel_cacheinfo_0x4()
[all …]
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| /arch/x86/kernel/cpu/resctrl/ |
| A D | internal.h | 133 } split; member
141 } split; member
150 } split; member
158 } split; member
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| A D | core.c | 193 hw_res->num_closid = edx.split.cos_max + 1; in __get_mem_config_intel()
194 max_delay = eax.split.max_delay + 1; in __get_mem_config_intel()
258 hw_res->num_closid = edx.split.cos_max + 1; in rdt_get_cache_alloc_cfg()
259 r->cache.cbm_len = eax.split.cbm_len + 1; in rdt_get_cache_alloc_cfg()
260 default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1; in rdt_get_cache_alloc_cfg()
263 r->cache.arch_has_sparse_bitmasks = ecx.split.noncont; in rdt_get_cache_alloc_cfg()
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| /arch/x86/events/amd/ |
| A D | lbr.c | 47 } split; member
58 } split; member
180 if ((!entry.to.split.valid && !entry.to.split.spec) || in amd_pmu_lbr_read()
181 entry.to.split.reserved) in amd_pmu_lbr_read()
186 br[out].from = sign_ext_branch_ip(entry.from.split.ip); in amd_pmu_lbr_read()
187 br[out].to = sign_ext_branch_ip(entry.to.split.ip); in amd_pmu_lbr_read()
188 br[out].mispred = entry.from.split.mispredict; in amd_pmu_lbr_read()
207 idx = (entry.to.split.valid << 1) | entry.to.split.spec; in amd_pmu_lbr_read()
431 x86_pmu.lbr_nr = ebx.split.lbr_v2_stack_sz; in amd_pmu_lbr_init()
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| A D | uncore.c | 73 } split; member
455 return info->split.cid; in amd_uncore_ctx_cid()
462 return info->split.gid; in amd_uncore_ctx_gid()
469 return info->split.num_pmcs; in amd_uncore_ctx_num_pmcs()
703 info.split.aux_data = 0; in amd_uncore_df_ctx_scan()
705 info.split.gid = 0; in amd_uncore_df_ctx_scan()
710 info.split.num_pmcs = ebx.split.num_df_pmc; in amd_uncore_df_ctx_scan()
839 info.split.aux_data = 0; in amd_uncore_l3_ctx_scan()
841 info.split.gid = 0; in amd_uncore_l3_ctx_scan()
1004 info.split.num_pmcs = ebx.split.num_umc_pmc; in amd_uncore_umc_ctx_scan()
[all …]
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| /arch/x86/include/asm/ |
| A D | perf_event.h | 164 } split; member
177 } split; member
188 } split; member
210 } split; member
221 } split; member
237 } split; member
249 } split; member
264 } split; member
282 } split; member
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| /arch/x86/kvm/vmx/ |
| A D | pmu_intel.c | 531 pmu->version = eax.split.version_id; in intel_pmu_refresh()
535 pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters, in intel_pmu_refresh()
537 eax.split.bit_width = min_t(int, eax.split.bit_width, in intel_pmu_refresh()
539 pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1; in intel_pmu_refresh()
540 eax.split.mask_length = min_t(int, eax.split.mask_length, in intel_pmu_refresh()
543 ((1ull << eax.split.mask_length) - 1); in intel_pmu_refresh()
548 pmu->nr_arch_fixed_counters = min_t(int, edx.split.num_counters_fixed, in intel_pmu_refresh()
550 edx.split.bit_width_fixed = min_t(int, edx.split.bit_width_fixed, in intel_pmu_refresh()
553 ((u64)1 << edx.split.bit_width_fixed) - 1; in intel_pmu_refresh()
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| /arch/x86/events/zhaoxin/ |
| A D | core.c | 522 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT - 1) in zhaoxin_pmu_init()
525 version = eax.split.version_id; in zhaoxin_pmu_init()
533 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0); in zhaoxin_pmu_init()
534 x86_pmu.cntval_bits = eax.split.bit_width; in zhaoxin_pmu_init()
535 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in zhaoxin_pmu_init()
537 x86_pmu.events_mask_len = eax.split.mask_length; in zhaoxin_pmu_init()
539 x86_pmu.fixed_cntr_mask64 = GENMASK_ULL(edx.split.num_counters_fixed - 1, 0); in zhaoxin_pmu_init()
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| /arch/x86/tools/ |
| A D | objdump_reformat.awk | 25 if (split($0, field, /: |\t/) < 3) {
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| A D | cpufeaturemasks.awk | 41 if (split($1, fs, "CONFIG_X86_|_FEATURE_") == 3)
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| /arch/x86/events/intel/ |
| A D | lbr.c | 1600 lbr_nr = fls(eax.split.lbr_depth_mask) * 8; in intel_pmu_arch_lbr_init()
1608 x86_pmu.lbr_depth_mask = eax.split.lbr_depth_mask; in intel_pmu_arch_lbr_init()
1609 x86_pmu.lbr_deep_c_reset = eax.split.lbr_deep_c_reset; in intel_pmu_arch_lbr_init()
1610 x86_pmu.lbr_lip = eax.split.lbr_lip; in intel_pmu_arch_lbr_init()
1611 x86_pmu.lbr_cpl = ebx.split.lbr_cpl; in intel_pmu_arch_lbr_init()
1612 x86_pmu.lbr_filter = ebx.split.lbr_filter; in intel_pmu_arch_lbr_init()
1613 x86_pmu.lbr_call_stack = ebx.split.lbr_call_stack; in intel_pmu_arch_lbr_init()
1614 x86_pmu.lbr_mispred = ecx.split.lbr_mispred; in intel_pmu_arch_lbr_init()
1615 x86_pmu.lbr_timed_lbr = ecx.split.lbr_timed_lbr; in intel_pmu_arch_lbr_init()
1616 x86_pmu.lbr_br_type = ecx.split.lbr_br_type; in intel_pmu_arch_lbr_init()
[all …]
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| /arch/arm64/boot/dts/renesas/ |
| A D | ulcb-kf.dtsi | 13 * // if you use xxxx-mix+split.dtsi
489 * #include "ulcb-kf-simple-audio-card-mix+split.dtsi"
491 * #include "ulcb-kf-audio-graph-card-mix+split.dtsi"
492 * #include "ulcb-kf-audio-graph-card2-mix+split.dtsi"
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| A D | ulcb.dtsi | 512 * #include "ulcb-simple-audio-card-mix+split.dtsi"
514 * #include "ulcb-audio-graph-card-mix+split.dtsi"
515 * #include "ulcb-audio-graph-card2-mix+split.dtsi"
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| A D | ulcb-kf-simple-audio-card-mix+split.dtsi | 41 label = "snd-kf-split";
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| /arch/riscv/boot/dts/sifive/ |
| A D | fu540-c000.dtsi | 62 tlb-split;
89 tlb-split;
116 tlb-split;
143 tlb-split;
|
| A D | fu740-c000.dtsi | 64 tlb-split;
91 tlb-split;
118 tlb-split;
145 tlb-split;
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| /arch/mips/mm/ |
| A D | tlbex.c | 1357 u32 *split; in build_r4000_tlb_refill_handler() local
1364 split = labels[i].addr; in build_r4000_tlb_refill_handler()
1370 split < p - MIPS64_REFILL_INSNS) in build_r4000_tlb_refill_handler()
1379 split = tlb_handler + MIPS64_REFILL_INSNS - 2; in build_r4000_tlb_refill_handler()
1386 if (uasm_insn_has_bdelay(relocs, split - 1)) in build_r4000_tlb_refill_handler()
1387 split--; in build_r4000_tlb_refill_handler()
1391 f += split - tlb_handler; in build_r4000_tlb_refill_handler()
1397 if (uasm_insn_has_bdelay(relocs, split)) in build_r4000_tlb_refill_handler()
1401 split, split + 1, f); in build_r4000_tlb_refill_handler()
1404 split++; in build_r4000_tlb_refill_handler()
[all …]
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| /arch/sh/cchips/ |
| A D | Kconfig | 28 # These will also be split into the Kconfig's below
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| /arch/riscv/boot/dts/microchip/ |
| A D | mpfs.dtsi | 59 tlb-split;
90 tlb-split;
121 tlb-split;
152 tlb-split;
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| /arch/x86/kvm/ |
| A D | cpuid.c | 1438 eax.split.version_id = kvm_pmu_cap.version; in __do_cpuid_func()
1439 eax.split.num_counters = kvm_pmu_cap.num_counters_gp; in __do_cpuid_func()
1440 eax.split.bit_width = kvm_pmu_cap.bit_width_gp; in __do_cpuid_func()
1441 eax.split.mask_length = kvm_pmu_cap.events_mask_len; in __do_cpuid_func()
1442 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed; in __do_cpuid_func()
1443 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed; in __do_cpuid_func()
1446 edx.split.anythread_deprecated = 1; in __do_cpuid_func()
1775 ebx.split.num_core_pmc = kvm_pmu_cap.num_counters_gp; in __do_cpuid_func()
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| /arch/arm64/boot/dts/mediatek/ |
| A D | mt6795.dtsi | 845 split0: split@14018000 {
846 compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split";
852 split1: split@14019000 {
853 compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split";
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| /arch/x86/kvm/svm/ |
| A D | pmu.c | 191 pmu->nr_arch_gp_counters = ebx.split.num_core_pmc; in amd_pmu_refresh()
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| /arch/arm64/tools/ |
| A D | gen-sysreg.awk | 70 } else if (split(bitdef, _bits, ":") == 2) {
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| /arch/riscv/boot/dts/starfive/ |
| A D | jh7100.dtsi | 40 tlb-split;
69 tlb-split;
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| /arch/arm/boot/dts/intel/ixp/ |
| A D | intel-ixp4xx-reference-design.dtsi | 70 intel,ixp4xx-eb-ahb-split-transfers = <0>;
|