Searched refs:until (Results 1 – 25 of 91) sorted by relevance
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107 u64 until = start + cycles; in delay_halt_tpause() local110 eax = lower_32_bits(until); in delay_halt_tpause()111 edx = upper_32_bits(until); in delay_halt_tpause()
89 /* Set .95V to prevent unstabilities until CPR for this SoC is done */93 /* Set always on until the CPU PLL is done */103 /* Hack this on until the gpu driver is ready for it */113 /* Set .95V to prevent unstabilities until CPR for this SoC is done */118 /* Set always on until the CPU PLL is done */
211 /* Set .95V to prevent unstabilities until CPR for this SoC is done */215 /* Set always on until the CPU PLL is done */225 /* Hack this on until the gpu driver is ready for it */240 /* Set .95V to prevent unstabilities until CPR for this SoC is done */245 /* Set always on until the CPU PLL is done */
151 /* Hack until we rig up the gpu consumer */433 dr_mode = "host"; /* Force to host until we have Type-C hooked up */
267 /* Hack until we rig up the gpu consumer */565 /* Force to peripheral until we can switch modes */570 /* Leave disabled until MSS is functional */
126 /* hack until we rig up the gpu consumer */388 dr_mode = "host"; /* Force to host until we have Type-C hooked up */
312 /* Hack until we rig up the gpu consumer */941 * Disable UFS until card quirks are in to avoid unrecoverable hard-brick958 /* Force to peripheral until we have Type-C hooked up */
27 beq 1002b @ wait until transmit done
48 beq 1002b @ wait until transmit done
29 beq 1001b @ wait until transmit done
89 | For denormalized numbers, shift the mantissa until the j-bit = 1,104 | Shifts the mantissa bits until msbit is set.128 lsll %d3,%d0 |shift ms mant until j-bit is set
18 | msb form a decimal digit. This process is iterated until43 | A7. Decrement d6 (LEN counter) and repeat the loop until zero.
71 // Temporary until code stops depending on it.74 // Temporary until get_immrbase() is fixed.
72 // Temporary until code stops depending on it.75 // Temporary until get_immrbase() is fixed.
95 // Temporary until code stops depending on it.
64 moveq #ICACHE_ONLY,%d0 | Cache disabled until we're ready to enable it
52 /* Not available until CPU deep sleep is implemented */
83 * missing during boot. Mark the domain as always on until the driver can
46 * missing during boot. Mark the domain as always on until the driver can
190 /* Not available until CPU deep sleep is implemented */239 /* Not available until CPU deep sleep is implemented */
15 @ TLS register update is deferred until return to user space
47 @ avoid accessing memory until this sequence is complete,
107 * in the boot process. Disable them until the issue is figured out.
65 @ division loop. Continue shifting until the divisor is 152 @ division loop. Continue shifting until the divisor is
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