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Searched refs:write_sysreg (Results 1 – 25 of 41) sorted by relevance

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/arch/arm64/include/asm/
A Darm_pmuv3.h23 write_sysreg(val, pmevcntr##n##_el0)
30 write_sysreg(val, pmevtyper##n##_el0)
67 write_sysreg(val, pmcr_el0); in write_pmcr()
77 write_sysreg(val, pmselr_el0); in write_pmselr()
82 write_sysreg(val, pmccntr_el0); in write_pmccntr()
102 write_sysreg(val, pmcntenset_el0); in write_pmcntenset()
107 write_sysreg(val, pmcntenclr_el0); in write_pmcntenclr()
112 write_sysreg(val, pmintenset_el1); in write_pmintenset()
122 write_sysreg(val, pmccfiltr_el0); in write_pmccfiltr()
142 write_sysreg(val, pmovsclr_el0); in write_pmovsclr()
[all …]
A Darch_timer.h105 write_sysreg(val, cntp_ctl_el0); in arch_timer_reg_write_cp15()
109 write_sysreg(val, cntp_cval_el0); in arch_timer_reg_write_cp15()
117 write_sysreg(val, cntv_ctl_el0); in arch_timer_reg_write_cp15()
121 write_sysreg(val, cntv_cval_el0); in arch_timer_reg_write_cp15()
166 write_sysreg(cntkctl, cntkctl_el1); in arch_timer_set_cntkctl()
A Dcpuidle.h20 write_sysreg(c->daif_bits | PSR_I_BIT | PSR_F_BIT, \
32 write_sysreg(c->daif_bits, daif); \
A Dmmu_context.h36 write_sysreg(task_pid_nr(next), contextidr_el1); in contextidr_thread_switch()
47 write_sysreg(ttbr, ttbr0_el1); in cpu_set_reserved_ttbr0_nosync()
81 write_sysreg(tcr, tcr_el1); in __cpu_set_tcr_t0sz()
141 write_sysreg(ttbr0, ttbr0_el1); in cpu_install_ttbr0()
A Ddaifflags.h117 write_sysreg(flags, daif); in local_daif_restore()
142 write_sysreg(flags, daif); in local_daif_inherit()
A Ddcc.h37 write_sysreg((unsigned char)c, dbgdtrtx_el0); in __dcc_putchar()
A Duaccess.h67 write_sysreg(ttbr - RESERVED_SWAPPER_OFFSET, ttbr0_el1); in __uaccess_ttbr0_disable()
69 write_sysreg(ttbr, ttbr1_el1); in __uaccess_ttbr0_disable()
90 write_sysreg(ttbr1, ttbr1_el1); in __uaccess_ttbr0_enable()
93 write_sysreg(ttbr0, ttbr0_el1); in __uaccess_ttbr0_enable()
A Dfpsimd.h39 write_sysreg(old | set, cpacr_el1); in cpacr_save_enable_kernel_sve()
49 write_sysreg(old | set, cpacr_el1); in cpacr_save_enable_kernel_sme()
56 write_sysreg(cpacr, cpacr_el1); in cpacr_restore()
/arch/arm64/kvm/hyp/include/hyp/
A Dsysreg-sr.h198 write_sysreg(*ctxt_mdscr_el1(ctxt), mdscr_el1); in __sysreg_restore_common_state()
207 write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0); in __sysreg_restore_user_state()
214 write_sysreg(midr, vpidr_el2); in __sysreg_restore_el1_state()
215 write_sysreg(mpidr, vmpidr_el2); in __sysreg_restore_el1_state()
256 write_sysreg(ctxt_sys_reg(ctxt, PAR_EL1), par_el1); in __sysreg_restore_el1_state()
257 write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL1), tpidr_el1); in __sysreg_restore_el1_state()
282 write_sysreg(ctxt_sys_reg(ctxt, SP_EL1), sp_el1); in __sysreg_restore_el1_state()
365 write_sysreg(vcpu->arch.ctxt.spsr_abt, spsr_abt); in __sysreg32_restore_state()
366 write_sysreg(vcpu->arch.ctxt.spsr_und, spsr_und); in __sysreg32_restore_state()
367 write_sysreg(vcpu->arch.ctxt.spsr_irq, spsr_irq); in __sysreg32_restore_state()
[all …]
A Dswitch.h63 write_sysreg(1 << 30, fpexc32_el2); in __activate_traps_fpsimd32()
84 write_sysreg(val, cptr_el2); in __activate_cptr_traps_nvhe()
152 write_sysreg(val, cpacr_el1); in __activate_cptr_traps_vhe()
175 write_sysreg(val, cptr_el2); in __deactivate_cptr_traps_nvhe()
187 write_sysreg(val, cpacr_el1); in __deactivate_cptr_traps_vhe()
418 write_sysreg(1 << 15, hstr_el2); in __activate_traps_common()
427 write_sysreg(0, pmselr_el0); in __activate_traps_common()
430 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0); in __activate_traps_common()
435 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2); in __activate_traps_common()
459 write_sysreg(0, hstr_el2); in __deactivate_traps_common()
[all …]
A Ddebug-sr.h19 #define write_debug(v,r,n) write_sysreg(v, r##n##_el1)
131 write_sysreg(ctxt_sys_reg(ctxt, MDCCINT_EL1), mdccint_el1); in __debug_restore_state()
A Dfault.h47 write_sysreg(par, par_el1); in __translate_far_to_hpfar()
/arch/arm/include/asm/
A Darm_pmuv3.h104 write_sysreg(val, PMEVCNTR##n)
138 write_sysreg(val, PMCR); in write_pmcr()
148 write_sysreg(val, PMSELR); in write_pmselr()
153 write_sysreg(val, PMCCNTR); in write_pmccntr()
170 write_sysreg(val, PMCNTENSET); in write_pmcntenset()
175 write_sysreg(val, PMCNTENCLR); in write_pmcntenclr()
180 write_sysreg(val, PMINTENSET); in write_pmintenset()
185 write_sysreg(val, PMINTENCLR); in write_pmintenclr()
190 write_sysreg(val, PMCCFILTR); in write_pmccfiltr()
202 write_sysreg(val, PMOVSR); in write_pmovsclr()
[all …]
A Darch_gicv3.h44 write_sysreg(val, a32); \
69 write_sysreg(val, ICC_DIR); in CPUIF_MAP()
84 write_sysreg(val, ICC_CTLR); in gic_write_ctlr()
95 write_sysreg(val, ICC_IGRPEN1); in gic_write_grpen1()
101 write_sysreg(val, ICC_SGI1R); in gic_write_sgi1r()
111 write_sysreg(val, ICC_SRE); in gic_write_sre()
117 write_sysreg(val, ICC_BPR1); in gic_write_bpr1()
127 write_sysreg(val, ICC_PMR); in gic_write_pmr()
/arch/arm64/kvm/hyp/nvhe/
A Dswitch.c56 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2); in __activate_traps()
101 write_sysreg(__kvm_hyp_host_vector, vbar_el2); in __deactivate_traps()
131 write_sysreg(pmu->events_host, pmcntenclr_el0); in __pmu_switch_to_guest()
134 write_sysreg(pmu->events_guest, pmcntenset_el0); in __pmu_switch_to_guest()
147 write_sysreg(pmu->events_guest, pmcntenclr_el0); in __pmu_switch_to_host()
150 write_sysreg(pmu->events_host, pmcntenset_el0); in __pmu_switch_to_host()
A Dtimer-sr.c16 write_sysreg(cntvoff, cntvoff_el2); in __kvm_timer_set_cntvoff()
/arch/arm/mm/
A Dpmsa-v7.c49 write_sysreg(v, RNGNR); in rgnr_write()
57 write_sysreg(v, DRACR); in dracr_write()
63 write_sysreg(v, DRSR); in drsr_write()
69 write_sysreg(v, DRBAR); in drbar_write()
81 write_sysreg(v, IRACR); in iracr_write()
87 write_sysreg(v, IRSR); in irsr_write()
93 write_sysreg(v, IRBAR); in irbar_write()
A Dpmsa-v8.c37 write_sysreg(v, PRSEL); in prsel_write()
42 write_sysreg(v, PRBAR); in prbar_write()
47 write_sysreg(v, PRLAR); in prlar_write()
A Dproc-v7-bugs.c48 write_sysreg(0, BPIALL); in harden_branch_predictor_bpiall()
53 write_sysreg(0, ICIALLU); in harden_branch_predictor_iciallu()
/arch/arm64/kvm/hyp/vhe/
A Dsysreg-sr.c90 write_sysreg(__vcpu_sys_reg(vcpu, PAR_EL1), par_el1); in __sysreg_restore_vel2_state()
91 write_sysreg(__vcpu_sys_reg(vcpu, TPIDR_EL1), tpidr_el1); in __sysreg_restore_vel2_state()
93 write_sysreg(ctxt_midr_el1(&vcpu->arch.ctxt), vpidr_el2); in __sysreg_restore_vel2_state()
94 write_sysreg(__vcpu_sys_reg(vcpu, MPIDR_EL1), vmpidr_el2); in __sysreg_restore_vel2_state()
142 write_sysreg(__vcpu_sys_reg(vcpu, SP_EL2), sp_el1); in __sysreg_restore_vel2_state()
A Dtimer-sr.c11 write_sysreg(cntvoff, cntvoff_el2); in __kvm_timer_set_cntvoff()
/arch/arm64/kernel/
A Ddebug-monitors.c45 write_sysreg(mdscr, mdscr_el1); in mdscr_write()
131 write_sysreg(0, osdlr_el1); in clear_os_lock()
132 write_sysreg(0, oslar_el1); in clear_os_lock()
A Dprocess.c253 write_sysreg(0, tpidr_el0); in tls_thread_flush()
266 write_sysreg(0, tpidrro_el0); in tls_thread_flush()
532 write_sysreg(next->thread.uw.tp_value, tpidrro_el0); in tls_thread_switch()
534 write_sysreg(0, tpidrro_el0); in tls_thread_switch()
536 write_sysreg(*task_user_tls(next), tpidr_el0); in tls_thread_switch()
A Dsys_compat.c98 write_sysreg(regs->regs[0], tpidrro_el0); in compat_arm_syscall()
/arch/arm/include/asm/vdso/
A Dcp15.h27 #define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__) macro

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