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Searched refs:CL (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
A Dsddr3.c72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
83 CL = ram->next->bios.timing_10_CL; in nvkm_sddr3_calc()
89 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; in nvkm_sddr3_calc()
101 CL = ramxlat(ramddr3_cl, CL); in nvkm_sddr3_calc()
103 if (CL < 0 || CWL < 0 || WR < 0) in nvkm_sddr3_calc()
108 ram->mr[0] |= (CL & 0x0e) << 3; in nvkm_sddr3_calc()
109 ram->mr[0] |= (CL & 0x01) << 2; in nvkm_sddr3_calc()
A Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
78 CL = ram->next->bios.timing_10_CL; in nvkm_gddr3_calc()
86 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; in nvkm_gddr3_calc()
102 CL = ramxlat(hi ? ramgddr3_cl_hi : ramgddr3_cl_lo, CL); in nvkm_gddr3_calc()
104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0) in nvkm_gddr3_calc()
109 ram->mr[0] |= (CL & 0x07) << 4; in nvkm_gddr3_calc()
110 ram->mr[0] |= (CL & 0x08) >> 1; in nvkm_gddr3_calc()
A Dsddr2.c63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
67 CL = ram->next->bios.timing_10_CL; in nvkm_sddr2_calc()
73 CL = (ram->next->bios.timing[1] & 0x0000001f); in nvkm_sddr2_calc()
86 CL = ramxlat(ramddr2_cl, CL); in nvkm_sddr2_calc()
88 if (CL < 0 || WR < 0) in nvkm_sddr2_calc()
93 ram->mr[0] |= (CL & 0x07) << 4; in nvkm_sddr2_calc()
A Dgddr5.c38 int WL, CL, WR, at[2], dt, ds; in nvkm_gddr5_calc() local
59 CL = (ram->next->bios.timing[1] & 0x0000001f); in nvkm_gddr5_calc()
70 if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35) in nvkm_gddr5_calc()
72 CL -= 5; in nvkm_gddr5_calc()
77 ram->mr[0] |= (CL & 0x0f) << 3; in nvkm_gddr5_calc()
119 ram->mr[8] |= (CL & 0x10) >> 4; in nvkm_gddr5_calc()
A Dramnv50.c88 T(CWL) = T(CL) - 1; in nv50_ram_timing_calc()
101 (0x2f + T(CL) - T(CWL)); in nv50_ram_timing_calc()
106 (0x2e + T(CL) - T(CWL)); in nv50_ram_timing_calc()
113 (3 + T(CL) - T(CWL)); in nv50_ram_timing_calc()
120 (T(CL) - 1) << 8 | in nv50_ram_timing_calc()
121 (T(CL) - 1); in nv50_ram_timing_calc()
134 timing[5] |= (T(CL) + 3) << 8; in nv50_ram_timing_calc()
135 timing[8] |= (T(CL) - 4); in nv50_ram_timing_calc()
138 timing[5] |= (T(CL) + 2) << 8; in nv50_ram_timing_calc()
139 timing[8] |= (T(CL) - 2); in nv50_ram_timing_calc()
[all …]
A Dramgt215.c364 T(CWL) = T(CL) - 1; in gt215_ram_timing_calc()
378 (5 + T(CL) - T(CWL)); in gt215_ram_timing_calc()
384 (0x30 + T(CL)) << 24 | in gt215_ram_timing_calc()
385 (0xb + T(CL)) << 8 | in gt215_ram_timing_calc()
386 (T(CL) - 1); in gt215_ram_timing_calc()
393 max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 | in gt215_ram_timing_calc()
395 timing[6] = (0x5a + T(CL)) << 16 | in gt215_ram_timing_calc()
396 max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 | in gt215_ram_timing_calc()
397 (0x50 + T(CL) - T(CWL)); in gt215_ram_timing_calc()
399 ((tUNK_base + T(CL)) << 16) | in gt215_ram_timing_calc()
[all …]
/drivers/video/fbdev/aty/
A Daty128fb.c325 u8 CL; member
340 .CL = 3,
354 .CL = 2,
368 .CL = 3,
1445 m->CL + in aty128_ddafifo()
/drivers/tty/vt/
A Ducs_width_table.h_shipped441 { 0x1F191, 0x1F19A }, /* SQUARED CL - SQUARED VS */

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