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Searched refs:CLK_TYPE_DIV6P1 (Results 1 – 2 of 2) sorted by relevance

/drivers/clk/renesas/
A Drenesas-cpg-mssr.h63 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */ enumerator
81 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
A Drenesas-cpg-mssr.c413 case CLK_TYPE_DIV6P1: in cpg_mssr_register_core_clk()
428 if (core->type == CLK_TYPE_DIV6P1) { in cpg_mssr_register_core_clk()

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