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Searched refs:COMPOSITE (Results 1 – 19 of 19) sorted by relevance

/drivers/clk/rockchip/
A Dclk-rk3576.c573 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_24m_p, 0,
636 COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0,
666 COMPOSITE(SCLK_UART0, "sclk_uart0", clk_uart_p, 0,
669 COMPOSITE(SCLK_UART2, "sclk_uart2", clk_uart_p, 0,
672 COMPOSITE(SCLK_UART3, "sclk_uart3", clk_uart_p, 0,
675 COMPOSITE(SCLK_UART4, "sclk_uart4", clk_uart_p, 0,
678 COMPOSITE(SCLK_UART5, "sclk_uart5", clk_uart_p, 0,
681 COMPOSITE(SCLK_UART6, "sclk_uart6", clk_uart_p, 0,
684 COMPOSITE(SCLK_UART7, "sclk_uart7", clk_uart_p, 0,
687 COMPOSITE(SCLK_UART8, "sclk_uart8", clk_uart_p, 0,
[all …]
A Dclk-rk3588.c1057 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
1062 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
1067 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0,
1075 COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0,
1162 COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0,
1196 COMPOSITE(CLK_TSADC, "clk_tsadc", gpll_24m_p, 0,
1448 COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0,
1454 COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0,
1565 COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0,
1568 COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0,
[all …]
A Dclk-rk3328.c309 COMPOSITE(0, "aclk_gpu_pre", mux_4plls_p, 0,
363 COMPOSITE(SCLK_TSP, "clk_tsp", mux_2plls_p, 0,
370 COMPOSITE(0, "clk_i2s0_div", mux_2plls_p, 0,
380 COMPOSITE(0, "clk_i2s1_div", mux_2plls_p, 0,
393 COMPOSITE(0, "clk_i2s2_div", mux_2plls_p, 0,
406 COMPOSITE(0, "clk_spdif_div", mux_2plls_p, 0,
441 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_2plls_p, 0,
444 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_2plls_p, 0,
462 COMPOSITE(SCLK_SPI, "clk_spi", mux_2plls_p, 0,
465 COMPOSITE(SCLK_PWM, "clk_pwm", mux_2plls_p, 0,
[all …]
A Dclk-rk3562.c233 COMPOSITE(ACLK_TOP_VIO, "aclk_top_vio", gpll_cpll_p, 0,
443 COMPOSITE(CLK_GPU_PRE, "clk_gpu_pre", gpll_cpll_p, 0,
456 COMPOSITE(CLK_NPU_PRE, "clk_npu_pre", gpll_cpll_p, 0,
562 COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0,
567 COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_xin24m_p, 0,
608 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0,
617 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0,
626 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0,
712 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
717 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
[all …]
A Dclk-rk3399.c548 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0,
583 COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
597 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
607 COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
617 COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
886 COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
997 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0,
1059 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0,
1131 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
1143 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0,
[all …]
A Dclk-rk3308.c380 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_dpll_vpll0_xin24m_p, 0,
383 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_dpll_vpll0_xin24m_p, 0,
386 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_dpll_vpll0_xin24m_p, 0,
389 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_dpll_vpll0_xin24m_p, 0,
393 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 0,
396 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_dpll_vpll0_xin24m_p, 0,
450 COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 0,
523 COMPOSITE(SCLK_SFC, "clk_sfc", mux_dpll_vpll0_vpll1_p, 0,
594 COMPOSITE(0, "clk_usbphy_ref_src", mux_dpll_vpll0_p, 0,
607 COMPOSITE(0, "clk_wifi_src", mux_wifi_src_p, 0,
[all …]
A Dclk-rv1108.c219 COMPOSITE(0, "aclk_rkvenc_pre", mux_pll_src_4plls_p, 0,
246 COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
249 COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
297 COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_wifi_src_p, 0,
346 COMPOSITE(SCLK_DSP, "sclk_dsp", mux_dsp_src_p, 0,
457 COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_4plls_p, 0,
481 COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_4plls_p, 0,
577 COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_2plls_p, 0,
627 COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0,
715 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
[all …]
A Dclk-rk3228.c226 COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
317 COMPOSITE(SCLK_RGA, "sclk_rga", mux_sclk_rga_p, 0,
325 COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0,
371 COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_2plls_p, 0,
382 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
417 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
427 COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
440 COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
450 COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0,
470 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_4plls_p, 0,
[all …]
A Dclk-px30.c431 COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0,
442 COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0,
504 COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0,
599 COMPOSITE(0, "clk_i2s0_tx_src", mux_gpll_npll_p, 0,
615 COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0,
631 COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0,
646 COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0,
687 COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0,
700 COMPOSITE(0, "clk_uart4_src", mux_uart_src_p, 0,
713 COMPOSITE(0, "clk_uart5_src", mux_uart_src_p, 0,
[all …]
A Dclk-rk3128.c235 COMPOSITE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
278 COMPOSITE(0, "clk_peri_src", mux_clk_peri_src_p, 0,
313 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
317 COMPOSITE(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0,
321 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
331 COMPOSITE(DCLK_VOP, "dclk_vop", mux_sclk_vop_src_p, 0,
334 COMPOSITE(SCLK_VOP, "sclk_vop", mux_sclk_vop_src_p, 0,
351 COMPOSITE(0, "i2s0_src", mux_pll_src_3plls_p, 0,
361 COMPOSITE(0, "i2s1_src", mux_pll_src_3plls_p, 0,
374 COMPOSITE(0, "sclk_spdif_src", mux_pll_src_3plls_p, 0,
[all …]
A Dclk-rv1126.c320 COMPOSITE(CLK_PWM0, "clk_pwm0", mux_xin24m_gpll_p, 0,
327 COMPOSITE(CLK_PWM1, "clk_pwm1", mux_xin24m_gpll_p, 0,
333 COMPOSITE(CLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
445 COMPOSITE(CLK_SCR1, "clk_scr1", mux_gpll_cpll_p, 0,
536 COMPOSITE(CLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
544 COMPOSITE(CLK_PWM2, "clk_pwm2", mux_xin24m_gpll_p, 0,
597 COMPOSITE(DCLK_DECOM, "dclk_decom", mux_gpll_cpll_p, 0,
603 COMPOSITE(CLK_CAN, "clk_can", mux_gpll_xin24m_p, 0,
726 COMPOSITE(ACLK_PDVO, "aclk_pdvo", mux_gpll_cpll_p, 0,
807 COMPOSITE(CLK_NANDC, "clk_nandc", mux_gpll_cpll_p, 0,
[all …]
A Dclk-rk3288.c360 COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
414 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,
417 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
526 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
529 COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
532 COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0,
535 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
551 COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
554 COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
623 COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
[all …]
A Dclk-rk3368.c367 COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
379 COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
388 COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
398 COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
443 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb_p, 0,
535 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
546 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
549 COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
552 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
585 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_cpll_gpll_p, 0,
[all …]
A Dclk-rk3568.c496 COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED,
539 COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0,
561 COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0,
739 COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0,
1027 COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0,
1032 COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0,
1093 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0,
1321 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
1326 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
1331 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0,
[all …]
A Dclk-rk3036.c212 COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
270 COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,
274 COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,
277 COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,
280 COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,
296 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
309 COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
322 COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
333 COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0,
337 COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0,
[all …]
A Dclk-rk3188.c287 COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
300 COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
317 COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
354 COMPOSITE(0, "mac_src", mux_mac_p, 0,
362 COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
575 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
579 COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
584 COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
601 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
694 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
[all …]
A Dclk-rk3528.c293 COMPOSITE(DCLK_VOP_SRC0, "dclk_vop_src0", mux_gpll_cpll_p, 0,
296 COMPOSITE(DCLK_VOP_SRC1, "dclk_vop_src1", mux_gpll_cpll_p, 0,
695 COMPOSITE(CLK_CAN0, "clk_can0", mux_gpll_cpll_p, 0,
698 COMPOSITE(CLK_CAN1, "clk_can1", mux_gpll_cpll_p, 0,
822 COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", mux_gpll_cpll_xin24m_p, 0,
887 COMPOSITE(CCLK_SRC_SDIO0, "cclk_src_sdio0", mux_gpll_cpll_xin24m_p, 0,
982 COMPOSITE(CLK_CAN3, "clk_can3", mux_gpll_cpll_p, 0,
989 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_gpll_cpll_xin24m_p, 0,
992 COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_gpll_cpll_xin24m_p, 0,
1006 COMPOSITE(CCLK_SRC_SDIO1, "cclk_src_sdio1", mux_gpll_cpll_xin24m_p, 0,
[all …]
A Dclk.h706 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ macro
/drivers/clk/stm32/
A Dclk-stm32mp1.c1766 COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,
1783 COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
1788 COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), 0,
1793 COMPOSITE(PLL2_Q, "pll2_q", PARENT("pll2"), 0,
1803 COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), 0,
1808 COMPOSITE(PLL3_Q, "pll3_q", PARENT("pll3"), 0,
1813 COMPOSITE(PLL3_R, "pll3_r", PARENT("pll3"), 0,
1818 COMPOSITE(PLL4_P, "pll4_p", PARENT("pll4"), 0,
1823 COMPOSITE(PLL4_Q, "pll4_q", PARENT("pll4"), 0,
1828 COMPOSITE(PLL4_R, "pll4_r", PARENT("pll4"), 0,
[all …]

Completed in 753 milliseconds