| /drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| A D | dcn35_pg_cntl.h | 34 SR(DOMAIN1_PG_CONFIG), \
65 PG_CNTL_SF(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
66 PG_CNTL_SF(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
140 uint32_t DOMAIN1_PG_CONFIG; member
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| A D | dcn35_pg_cntl.c | 220 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); in pg_cntl35_hubp_dpp_pg_control()
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| /drivers/gpu/drm/amd/display/dc/hwss/dce/ |
| A D | dce_hwseq.h | 234 SR(DOMAIN1_PG_CONFIG), \
278 SR(DOMAIN1_PG_CONFIG), \
342 SR(DOMAIN1_PG_CONFIG), \
450 SR(DOMAIN1_PG_CONFIG), \
502 SR(DOMAIN1_PG_CONFIG), \
599 uint32_t DOMAIN1_PG_CONFIG; member
810 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
845 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
906 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
958 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
[all …]
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn302/ |
| A D | dcn302_hwseq.c | 52 if (REG(DOMAIN1_PG_CONFIG) == 0) in dcn302_dpp_pg_control()
57 REG_UPDATE(DOMAIN1_PG_CONFIG, in dcn302_dpp_pg_control()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| A D | dcn36_resource.h | 52 SR(DOMAIN1_PG_CONFIG), \
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| A D | dcn36_resource.c | 544 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
545 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| A D | dcn31_hwseq.c | 362 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); in dcn31_enable_power_gating_plane()
468 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn31_hubp_pg_control()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 705 SR(DOMAIN1_PG_CONFIG), \
739 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
740 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.h | 196 SR(DOMAIN1_PG_CONFIG), \
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| A D | dcn35_resource.c | 563 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
564 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 718 SR(DOMAIN1_PG_CONFIG), \
754 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
755 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 711 SR(DOMAIN1_PG_CONFIG), \
745 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
746 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 558 SR(DOMAIN1_PG_CONFIG), \
593 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
594 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 710 SR(DOMAIN1_PG_CONFIG), \
744 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
745 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| A D | dcn314_hwseq.c | 310 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); in dcn314_enable_power_gating_plane()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 537 SR(DOMAIN1_PG_CONFIG), \
575 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
576 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 562 SR(DOMAIN1_PG_CONFIG), \
597 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
598 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| A D | dcn32_hwseq.c | 149 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); in dcn32_enable_power_gating_plane()
180 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn32_hubp_pg_control()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 543 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
544 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 332 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); in dcn20_enable_power_gating_plane()
561 if (REG(DOMAIN1_PG_CONFIG) == 0) in dcn20_dpp_pg_control()
566 REG_UPDATE(DOMAIN1_PG_CONFIG, in dcn20_dpp_pg_control()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 811 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); in dcn10_enable_power_gating_plane()
869 if (REG(DOMAIN1_PG_CONFIG) == 0) in dcn10_dpp_pg_control()
874 REG_UPDATE(DOMAIN1_PG_CONFIG, in dcn10_dpp_pg_control()
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| /drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| A D | dcn35_hwseq.c | 578 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); in dcn35_enable_power_gating_plane()
|