| /drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| A D | dcn35_pg_cntl.h | 48 SR(DOMAIN3_PG_STATUS), \
93 PG_CNTL_SF(DOMAIN3_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \
94 PG_CNTL_SF(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
154 uint32_t DOMAIN3_PG_STATUS; member
|
| A D | dcn35_pg_cntl.c | 175 REG_GET(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); in pg_cntl35_hubp_dpp_pg_status()
231 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in pg_cntl35_hubp_dpp_pg_control()
|
| /drivers/gpu/drm/amd/display/dc/hwss/dce/ |
| A D | dce_hwseq.h | 244 SR(DOMAIN3_PG_STATUS), \
298 SR(DOMAIN3_PG_STATUS), \
355 SR(DOMAIN3_PG_STATUS), \
463 SR(DOMAIN3_PG_STATUS), \
519 SR(DOMAIN3_PG_STATUS), \
619 uint32_t DOMAIN3_PG_STATUS; member
826 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
881 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
928 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
980 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
[all …]
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| A D | dcn36_resource.h | 62 SR(DOMAIN3_PG_STATUS), \
|
| A D | dcn36_resource.c | 569 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
|
| /drivers/gpu/drm/amd/display/dc/hwss/dcn302/ |
| A D | dcn302_hwseq.c | 68 REG_WAIT(DOMAIN3_PG_STATUS, in dcn302_dpp_pg_control()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.h | 206 SR(DOMAIN3_PG_STATUS), \
|
| A D | dcn35_resource.c | 588 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 714 SR(DOMAIN3_PG_STATUS), \
754 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
|
| /drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| A D | dcn31_hwseq.c | 477 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn31_hubp_pg_control()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 728 SR(DOMAIN3_PG_STATUS), \
771 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 720 SR(DOMAIN3_PG_STATUS), \
760 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 568 SR(DOMAIN3_PG_STATUS), \
610 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 719 SR(DOMAIN3_PG_STATUS), \
759 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 551 SR(DOMAIN3_PG_STATUS), \
600 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 572 SR(DOMAIN3_PG_STATUS), \
614 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
|
| /drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| A D | dcn32_hwseq.c | 189 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn32_hubp_pg_control()
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 568 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
|
| /drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 577 REG_WAIT(DOMAIN3_PG_STATUS, in dcn20_dpp_pg_control()
|
| /drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 885 REG_WAIT(DOMAIN3_PG_STATUS, in dcn10_dpp_pg_control()
|