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Searched refs:DP0_PLLCTRL (Results 1 – 1 of 1) sorted by relevance

/drivers/gpu/drm/bridge/
A Dtc358767.c320 #define DP0_PLLCTRL 0x0900 macro
798 ret = tc_pllupdate(tc, DP0_PLLCTRL); in tc_aux_link_setup()
1136 ret = tc_pllupdate(tc, DP0_PLLCTRL); in tc_main_link_enable()
1446 ret = tc_pllupdate(tc, DP0_PLLCTRL); in tc_dpi_stream_enable()
2129 case DP0_PLLCTRL: in tc_readable_reg()
2169 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),

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