Searched refs:DSCC_PPS_CONFIG0 (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| A D | dcn20_dsc.h | 41 SRI(DSCC_PPS_CONFIG0, DSCC, id),\
474 uint32_t DSCC_PPS_CONFIG0; member
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| A D | dcn20_dsc.c | 623 REG_SET_3(DSCC_PPS_CONFIG0, 0, in dsc_write_to_registers()
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| /drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| A D | dcn401_dsc.c | 245 REG_SET_3(DSCC_PPS_CONFIG0, 0, in dsc_write_to_registers()
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| A D | dcn401_dsc.h | 212 uint32_t DSCC_PPS_CONFIG0; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.h | 425 SRI_ARR(DSCC_PPS_CONFIG0, DSCC, id), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 730 SRI_ARR(DSCC_PPS_CONFIG0, DSCC, id), \
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