| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_mode_vba_util_32.h | 224 bool DSCEnable,
267 bool DSCEnable,
297 bool DSCEnable,
310 bool DSCEnable,
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| A D | display_mode_vba_util_32.c | 1189 bool DSCEnable, in dml32_CalculateODMMode() argument
1232 (DSCEnable && (HActive > 2 * MaximumPixelsPerLinePerDSCUnit)) in dml32_CalculateODMMode()
1244 (DSCEnable && (HActive > MaximumPixelsPerLinePerDSCUnit)) in dml32_CalculateODMMode()
1354 bool DSCEnable, in dml32_CalculateOutputLink() argument
1386 if (DSCEnable == true) { in dml32_CalculateOutputLink()
1580 bool DSCEnable, in dml32_TruncToValidBPP() argument
1633 } else if (DSCEnable && Output == dm_dp) { in dml32_TruncToValidBPP()
1639 if (DSCEnable) { in dml32_TruncToValidBPP()
1658 if (DSCEnable) { in dml32_TruncToValidBPP()
1688 bool DSCEnable, in dml32_RequiredDTBCLK() argument
[all …]
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| A D | display_mode_vba_32.c | 2105 mode_lib->vba.DSCEnable[k], in dml32_ModeSupportAndSystemConfigurationFull()
2361 if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.ForcedOutputLinkBPP[k] != 0) in dml32_ModeSupportAndSystemConfigurationFull()
2363 if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.OutputFormat[k] == dm_n422 in dml32_ModeSupportAndSystemConfigurationFull()
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_utils.c | 125 dml_output_array->DSCEnable[dst_index] = dml_output_array->DSCEnable[src_index]; in dml2_util_copy_dml_output()
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| A D | display_mode_core.c | 92 enum dml_dsc_enable DSCEnable,
112 dml_bool_t DSCEnable,
381 dml_bool_t DSCEnable,
443 dml_bool_t DSCEnable,
2713 dml_bool_t DSCEnable, in TruncToValidBPP() argument
2772 if (DSCEnable) { in TruncToValidBPP()
2793 if (DSCEnable) { in TruncToValidBPP()
4576 dml_bool_t DSCEnable, in RequiredDTBCLK() argument
4586 if (DSCEnable != true) { in RequiredDTBCLK()
5359 enum dml_dsc_enable DSCEnable, in CalculateOutputLink() argument
[all …]
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| A D | display_mode_core_structs.h | 628 …enum dml_dsc_enable DSCEnable[__DML_NUM_PLANES__]; //< brief for mode support check; use to determ… member
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| A D | dml2_translation_helper.c | 784 out->DSCEnable[location] = (enum dml_dsc_enable)in->timing.flags.DSC; in populate_dml_output_cfg_from_stream_state()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_mode_vba_31.c | 3588 bool DSCEnable, argument
3631 if (DSCEnable && Output == dm_dp) {
3644 if (DSCEnable) {
3664 …if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP <…
3665 || (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) {
4310 if (v->DSCEnable[k] == true) {
4347 v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
4389 v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
4430 if (v->Outbpp == BPP_INVALID && v->DSCEnable[k] == true &&
4545 if (v->DSCEnable[k] == true && v->OutputFormat[k] == dm_n422
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_mode_vba_314.c | 3694 bool DSCEnable, argument
3737 if (DSCEnable && Output == dm_dp) {
3750 if (DSCEnable) {
3770 …if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP <…
3771 || (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) {
4397 if (v->DSCEnable[k] == true) {
4434 v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
4476 v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
4517 if (v->Outbpp == BPP_INVALID && v->DSCEnable[k] == true &&
4632 if (v->DSCEnable[k] == true && v->OutputFormat[k] == dm_n422
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_dcn4_calcs.c | 1263 bool DSCEnable, in TruncToValidBPP() argument
1316 } else if (DSCEnable && Output == dml2_dp) { in TruncToValidBPP()
1322 ODMMode = DSCEnable ? ODMModeDSC : ODMModeNoDSC; in TruncToValidBPP()
1329 if (DSCEnable) { in TruncToValidBPP()
4101 bool DSCEnable, in CalculateODMMode() argument
4123 bool UseDSC = DSCEnable && (NumberOfDSCSlices > 0); in CalculateODMMode()
4209 enum dml2_dsc_enable_option DSCEnable, in CalculateOutputLink() argument
4252 if (DSCEnable == dml2_dsc_enable) { in CalculateOutputLink()
4365 if (DSCEnable == dml2_dsc_enable) { in CalculateOutputLink()
4453 bool DSCEnable, in RequiredDTBCLK() argument
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_vba.h | 1072 bool DSCEnable[DC__NUM_DPP__MAX]; member
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| A D | display_mode_vba.c | 648 mode_lib->vba.DSCEnable[mode_lib->vba.NumberOfActivePlanes] = dout->dsc_enable; in fetch_pipe_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_mode_vba_30.c | 3444 bool DSCEnable, in TruncToValidBPP() argument
3486 if (DSCEnable && Output == dm_dp) { in TruncToValidBPP()
3500 if (DSCEnable) { in TruncToValidBPP()
3520 …if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP =… in TruncToValidBPP()
3521 (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) { in TruncToValidBPP()
4066 if (v->DSCEnable[k] == true) { in dml30_ModeSupportAndSystemConfigurationFull()
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