Searched refs:DSC_TOP_CONTROL (Results 1 – 7 of 7) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dsc/dcn35/ |
| A D | dcn35_dsc.c | 94 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc35_enable()
101 REG_UPDATE(DSC_TOP_CONTROL, in dsc35_enable()
111 REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable); in dsc35_set_fgcg()
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| /drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| A D | dcn401_dsc.c | 99 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); in dsc401_read_state()
147 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc401_enable()
154 REG_UPDATE(DSC_TOP_CONTROL, in dsc401_enable()
170 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc401_disable()
178 REG_UPDATE(DSC_TOP_CONTROL, in dsc401_disable()
392 REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable); in dsc401_set_fgcg()
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| A D | dcn401_dsc.h | 203 uint32_t DSC_TOP_CONTROL; member
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| /drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| A D | dcn20_dsc.c | 146 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); in dsc2_read_state()
228 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc2_enable()
235 REG_UPDATE(DSC_TOP_CONTROL, in dsc2_enable()
251 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc2_disable()
259 REG_UPDATE(DSC_TOP_CONTROL, in dsc2_disable()
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| A D | dcn20_dsc.h | 35 SRI(DSC_TOP_CONTROL, DSC_TOP, id),\
468 uint32_t DSC_TOP_CONTROL; member
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| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.h | 417 SRI_ARR(DSC_TOP_CONTROL, DSC_TOP, id), \
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 725 SRI_ARR(DSC_TOP_CONTROL, DSC_TOP, id), \
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Completed in 19 milliseconds