Searched refs:TRSL_ID_AXI4_MASTER_0 (Results 1 – 2 of 2) sorted by relevance
100 #define TRSL_ID_AXI4_MASTER_0 0x00000004u macro
639 writel(TRSL_ID_AXI4_MASTER_0, table_addr + ATR0_PCIE_WIN0_TRSL_PARAM); in mc_pcie_setup_inbound_atr()
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