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Searched refs:__initconst (Results 1 – 25 of 390) sorted by relevance

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/drivers/clk/ti/
A Dclk-7xx.c32 static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
56 static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
81 static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
117 static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
149 static const char * const dra7_cam_gfclk_mux_parents[] __initconst = {
212 static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
261 static const char * const dra7_dss_dss_clk_parents[] __initconst = {
271 static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
307 static const char * const dra7_gpu_core_mux_parents[] __initconst = {
314 static const char * const dra7_gpu_hyd_mux_parents[] __initconst = {
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A Dclk-44xx.c44 static const char * const omap4_aess_fclk_parents[] __initconst = {
263 static const char * const omap4_iss_ctrlclk_parents[] __initconst = {
273 static const char * const omap4_fdif_fck_parents[] __initconst = {
294 static const char * const omap4_dss_dss_clk_parents[] __initconst = {
304 static const char * const omap4_dss_sys_clk_parents[] __initconst = {
309 static const char * const omap4_dss_tv_clk_parents[] __initconst = {
327 static const char * const omap4_sgx_clk_mux_parents[] __initconst = {
343 static const char * const omap4_hsmmc1_fclk_parents[] __initconst = {
359 static const char * const omap4_hsi_fck_parents[] __initconst = {
651 static const int omap4_trace_clk_div_div_ck_divs[] __initconst = {
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A Dclk-54xx.c38 static const char * const omap5_aess_fclk_parents[] __initconst = {
52 static const char * const omap5_dmic_gfclk_parents[] __initconst = {
59 static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
72 static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
85 static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
98 static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
230 static const char * const omap5_gpio2_dbclk_parents[] __initconst = {
307 omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = {
391 static const char * const omap5_mmc1_fclk_parents[] __initconst = {
407 static const char * const omap5_mmc2_fclk_parents[] __initconst = {
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A Dclk-33xx.c18 static const char * const am3_gpio1_dbclk_parents[] __initconst = {
23 static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
28 static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
33 static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
38 static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = {
121 static const char * const am3_gpio0_dbclk_parents[] __initconst = {
145 static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
156 static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
166 static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
176 static const char * const am3_dbg_clka_ck_parents[] __initconst = {
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A Dclk-43xx.c18 static const struct omap_clkctrl_reg_data am4_l3s_tsc_clkctrl_regs[] __initconst = {
23 static const char * const am4_synctimer_32kclk_parents[] __initconst = {
28 static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
39 static const char * const am4_gpio0_dbclk_parents[] __initconst = {
44 static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
62 static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
77 static const struct omap_clkctrl_reg_data am4_l3_clkctrl_regs[] __initconst = {
92 static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
126 static const char * const am4_gpio1_dbclk_parents[] __initconst = {
220 const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = {
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/drivers/soc/renesas/
A Drenesas-soc.c20 static const struct renesas_family fam_rcar_gen1 __initconst __maybe_unused = {
44 static const struct renesas_family fam_rza1 __initconst __maybe_unused = {
48 static const struct renesas_family fam_rza2 __initconst __maybe_unused = {
56 static const struct renesas_family fam_rzg1 __initconst __maybe_unused = {
61 static const struct renesas_family fam_rzg2 __initconst __maybe_unused = {
92 static const struct renesas_soc soc_rz_a1h __initconst __maybe_unused = {
408 static const struct renesas_id id_bsid __initconst = { variable
417 static const struct renesas_id id_rzg2l __initconst = { variable
422 static const struct renesas_id id_rzv2m __initconst = { variable
427 static const struct renesas_id id_prr __initconst = { variable
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/drivers/clk/mediatek/
A Dclk-mt7986-topckgen.c70 static const char *const spinfi_parents[] __initconst = {
76 static const char *const spi_parents[] __initconst = {
86 static const char *const pwm_parents[] __initconst = {
90 static const char *const i2c_parents[] __initconst = {
94 static const char *const pextp_tl_ck_parents[] __initconst = {
98 static const char *const emmc_250m_parents[] __initconst = {
119 static const char *const arm_db_main_parents[] __initconst = {
133 static const char *const netsys_mcu_parents[] __initconst = {
138 static const char *const netsys_2x_parents[] __initconst = {
145 static const char *const sgm_reg_parents[] __initconst = {
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A Dclk-mt7981-topckgen.c101 static const char * const nfi1x_parents[] __initconst = {
112 static const char * const spinfi_parents[] __initconst = {
123 static const char * const spi_parents[] __initconst = {
134 static const char * const uart_parents[] __initconst = {
140 static const char * const pwm_parents[] __initconst = {
149 static const char * const i2c_parents[] __initconst = {
191 static const char * const sysaxi_parents[] __initconst = {
253 static const char * const aud_parents[] __initconst = {
258 static const char * const a1sys_parents[] __initconst = {
263 static const char * const aud_l_parents[] __initconst = {
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A Dclk-mt8516.c23 static const struct mtk_fixed_clk fixed_clks[] __initconst = {
75 static const char * const uart0_parents[] __initconst = {
96 static const char * const msdc0_parents[] __initconst = {
107 static const char * const uart1_parents[] __initconst = {
112 static const char * const msdc1_parents[] __initconst = {
266 static const char * const eth_parents[] __initconst = {
274 static const char * const aud1_parents[] __initconst = {
298 static const char * const i2c_parents[] __initconst = {
310 static const char * const pwm_parents[] __initconst = {
315 static const char * const spi_parents[] __initconst = {
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/drivers/pinctrl/samsung/
A Dpinctrl-exynos-arm64.c392 static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
571 static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
625 const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { variable
698 static const struct samsung_pin_ctrl exynos7870_pin_ctrl[] __initconst = {
806 static const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = {
899 static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = {
1034 static const struct samsung_pin_ctrl exynos990_pin_ctrl[] __initconst = {
1651 static const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = {
1673 const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { variable
1759 static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
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A Dpinctrl-exynos-arm.c104 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
142 static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
156 const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = { variable
225 static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
246 const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = { variable
337 static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
434 static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
539 static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
627 static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
732 static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
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/drivers/soc/rockchip/
A Dgrf.c30 static const struct rockchip_grf_value rk3036_defaults[] __initconst = {
38 static const struct rockchip_grf_info rk3036_grf __initconst = { variable
51 static const struct rockchip_grf_info rk3128_grf __initconst = { variable
62 static const struct rockchip_grf_info rk3228_grf __initconst = { variable
75 static const struct rockchip_grf_info rk3288_grf __initconst = { variable
86 static const struct rockchip_grf_info rk3328_grf __initconst = { variable
97 static const struct rockchip_grf_info rk3368_grf __initconst = { variable
108 static const struct rockchip_grf_info rk3399_grf __initconst = { variable
133 static const struct rockchip_grf_info rk3576_sysgrf __initconst = { variable
144 static const struct rockchip_grf_info rk3576_iocgrf __initconst = { variable
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/drivers/clk/samsung/
A Dclk-s5pv210.c128 static const char *const fin_pll_p[] __initconst = {
133 static const char *const mout_apll_p[] __initconst = {
138 static const char *const mout_mpll_p[] __initconst = {
143 static const char *const mout_epll_p[] __initconst = {
153 static const char *const mout_vpll_p[] __initconst = {
158 static const char *const mout_group1_p[] __initconst = {
213 static const char *const mout_spdif_p[] __initconst = {
229 static const char *const mout_flash_p[] __initconst = {
234 static const char *const mout_dac_p[] __initconst = {
239 static const char *const mout_hdmi_p[] __initconst = {
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A Dclk-exynos7.c67 static const unsigned long topc_clk_regs[] __initconst = {
254 static const unsigned long top0_clk_regs[] __initconst = {
436 static const unsigned long top1_clk_regs[] __initconst = {
595 static const unsigned long ccore_clk_regs[] __initconst = {
637 static const unsigned long peric0_clk_regs[] __initconst = {
713 static const unsigned long peric1_clk_regs[] __initconst = {
829 static const unsigned long peris_clk_regs[] __initconst = {
902 static const unsigned long fsys0_clk_regs[] __initconst = {
1018 static const unsigned long fsys1_clk_regs[] __initconst = {
1123 static const unsigned long mscl_clk_regs[] __initconst = {
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A Dclk-exynos5260.c90 static const unsigned long aud_clk_regs[] __initconst = {
143 static const struct samsung_cmu_info aud_cmu __initconst = { variable
166 static const unsigned long disp_clk_regs[] __initconst = {
356 static const unsigned long egl_clk_regs[] __initconst = {
420 static const unsigned long fsys_clk_regs[] __initconst = {
520 static const unsigned long g2d_clk_regs[] __initconst = {
611 static const unsigned long g3d_clk_regs[] __initconst = {
807 static const unsigned long isp_clk_regs[] __initconst = {
926 static const unsigned long kfc_clk_regs[] __initconst = {
990 static const unsigned long mfc_clk_regs[] __initconst = {
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A Dclk-exynos850.c132 static const unsigned long top_clk_regs[] __initconst = {
610 static const unsigned long apm_clk_regs[] __initconst = {
775 static const unsigned long aud_clk_regs[] __initconst = {
1019 static const unsigned long cmgp_clk_regs[] __initconst = {
1128 static const unsigned long cpucl0_clk_regs[] __initconst = {
1488 static const unsigned long g3d_clk_regs[] __initconst = {
1587 static const unsigned long hsi_clk_regs[] __initconst = {
1695 static const unsigned long is_clk_regs[] __initconst = {
1949 static const unsigned long peri_clk_regs[] __initconst = {
2120 static const unsigned long core_clk_regs[] __initconst = {
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A Dclk-exynosautov9.c196 static const unsigned long top_clk_regs[] __initconst = {
945 static const struct samsung_cmu_info top_cmu_info __initconst = { variable
978 static const unsigned long busmc_clk_regs[] __initconst = {
1032 static const unsigned long core_clk_regs[] __initconst = {
1093 static const unsigned long dpum_clk_regs[] __initconst = {
1205 static const unsigned long fsys0_clk_regs[] __initconst = {
1426 static const unsigned long fsys1_clk_regs[] __initconst = {
1537 static const unsigned long fsys2_clk_regs[] __initconst = {
1637 static const unsigned long peric0_clk_regs[] __initconst = {
1892 static const unsigned long peric1_clk_regs[] __initconst = {
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A Dclk-exynosautov920.c183 static const unsigned long top_clk_regs[] __initconst = {
989 static const struct samsung_cmu_info top_cmu_info __initconst = { variable
1035 static const unsigned long cpucl0_clk_regs[] __initconst = {
1161 static const unsigned long cpucl1_clk_regs[] __initconst = {
1263 static const unsigned long cpucl2_clk_regs[] __initconst = {
1373 static const unsigned long peric0_clk_regs[] __initconst = {
1513 static const unsigned long peric1_clk_regs[] __initconst = {
1634 static const unsigned long misc_clk_regs[] __initconst = {
1685 static const unsigned long hsi0_clk_regs[] __initconst = {
1723 static const unsigned long hsi1_clk_regs[] __initconst = {
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A Dclk-fsd.c94 static const unsigned long cmu_clk_regs[] __initconst = {
173 static const struct samsung_pll_clock cmu_pll_clks[] __initconst = {
197 static const struct samsung_mux_clock cmu_mux_clks[] __initconst = {
212 static const struct samsung_div_clock cmu_div_clks[] __initconst = {
303 static const struct samsung_cmu_info cmu_cmu_info __initconst = { variable
408 static const unsigned long peric_clk_regs[] __initconst = {
741 static const unsigned long fsys0_clk_regs[] __initconst = {
1015 static const unsigned long fsys1_clk_regs[] __initconst = {
1216 static const unsigned long imem_clk_regs[] __initconst = {
1460 static const unsigned long mfc_clk_regs[] __initconst = {
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A Dclk-exynos5433.c136 static const unsigned long top_clk_regs[] __initconst = {
847 static const unsigned long cpif_clk_regs[] __initconst = {
995 static const unsigned long mif_clk_regs[] __initconst = {
2029 static const unsigned long fsys_clk_regs[] __initconst = {
2384 static const unsigned long g2d_clk_regs[] __initconst = {
2527 static const unsigned long disp_clk_regs[] __initconst = {
2938 static const unsigned long aud_clk_regs[] __initconst = {
3117 static const unsigned long bus2_clk_regs[] __initconst = {
3271 static const unsigned long g3d_clk_regs[] __initconst = {
4158 static const unsigned long mfc_clk_regs[] __initconst = {
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A Dclk-exynos7870.c154 static const unsigned long mif_clk_regs[] __initconst = {
297 static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
722 static const struct samsung_cmu_info mif_cmu_info __initconst = { variable
786 static const unsigned long dispaud_clk_regs[] __initconst = {
1038 static const unsigned long fsys_clk_regs[] __initconst = {
1159 static const unsigned long g3d_clk_regs[] __initconst = {
1239 static const struct samsung_cmu_info g3d_cmu_info __initconst = { variable
1286 static const unsigned long isp_clk_regs[] __initconst = {
1424 static const struct samsung_cmu_info isp_cmu_info __initconst = { variable
1456 static const unsigned long mfcmscl_clk_regs[] __initconst = {
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A Dclk-exynos7885.c91 static const unsigned long top_clk_regs[] __initconst = {
156 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
195 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
243 static const struct samsung_div_clock top_div_clks[] __initconst = {
343 static const struct samsung_cmu_info top_cmu_info __initconst = { variable
413 static const unsigned long peri_clk_regs[] __initconst = {
566 static const struct samsung_cmu_info peri_cmu_info __initconst = { variable
604 static const unsigned long core_clk_regs[] __initconst = {
673 static const struct samsung_cmu_info core_cmu_info __initconst = { variable
709 static const unsigned long fsys_clk_regs[] __initconst = {
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/drivers/clk/hisilicon/
A Dclk-hi3620.c24 static const char *const timer0_mux_p[] __initconst = { "osc32k", "timerclk01", };
34 static const char *const uart0_mux_p[] __initconst = { "osc26m", "pclk", };
35 static const char *const uart1_mux_p[] __initconst = { "osc26m", "pclk", };
36 static const char *const uart2_mux_p[] __initconst = { "osc26m", "pclk", };
37 static const char *const uart3_mux_p[] __initconst = { "osc26m", "pclk", };
38 static const char *const uart4_mux_p[] __initconst = { "osc26m", "pclk", };
44 static const char *const pwm0_mux_p[] __initconst = { "osc32k", "osc26m", };
45 static const char *const pwm1_mux_p[] __initconst = { "osc32k", "osc26m", };
46 static const char *const sd_mux_p[] __initconst = { "armpll2", "armpll3", };
54 static const char *const ldi0_mux_p[] __initconst = { "armpll2", "armpll4",
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/drivers/platform/x86/x86-android-tablets/
A Dother.c90 const struct x86_dev_info acer_b1_750_info __initconst = { variable
117 const struct x86_dev_info advantech_mica_071_info __initconst = { variable
202 const struct x86_dev_info chuwi_hi8_info __initconst = { variable
242 const struct x86_dev_info cyberbook_t116_info __initconst = { variable
276 const struct x86_dev_info czc_p10t __initconst = { variable
424 const struct x86_dev_info nextbook_ares8_info __initconst = { variable
491 const struct x86_dev_info nextbook_ares8a_info __initconst = { variable
516 const struct x86_dev_info peaq_c1010_info __initconst = { variable
655 const struct x86_dev_info vexia_edu_atla10_5v_info __initconst = { variable
823 const struct x86_dev_info vexia_edu_atla10_9v_info __initconst = { variable
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/drivers/clk/mvebu/
A Dmv98dx3236.c50 static const u32 mv98dx3236_cpu_frequencies[] __initconst = {
60 static const u32 mv98dx4251_cpu_frequencies[] __initconst = {
92 static const struct coreclk_ratio mv98dx3236_core_ratios[] __initconst = {
97 static const int __initconst mv98dx3236_cpu_mpll_ratios[8][2] = {
102 static const int __initconst mv98dx3236_cpu_ddr_ratios[8][2] = {
107 static const int __initconst mv98dx4251_cpu_mpll_ratios[8][2] = {
112 static const int __initconst mv98dx4251_cpu_ddr_ratios[8][2] = {
158 static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {

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