| /drivers/rtc/ |
| A D | rtc-stm32.c | 146 u16 cfgr; member
256 unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr); in stm32_rtc_pinmux_action_alarm() local
286 writel_relaxed(cfgr, rtc->base + regs.cfgr); in stm32_rtc_pinmux_action_alarm()
297 unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr); in stm32_rtc_pinmux_lsco_available() local
822 .cfgr = UNDEF_REG,
848 .cfgr = UNDEF_REG,
883 .cfgr = 0x60,
909 .cfgr = 0x60,
942 if (regs.cfgr != UNDEF_REG) { in stm32_rtc_clean_outs()
943 unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr); in stm32_rtc_clean_outs() local
[all …]
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| /drivers/pwm/ |
| A D | pwm-stm32-lp.c | 96 u32 cfgr, presc; in stm32_pwm_lp_compare_channel_apply() local
108 ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); in stm32_pwm_lp_compare_channel_apply()
111 presc = FIELD_GET(STM32_LPTIM_PRESC, cfgr); in stm32_pwm_lp_compare_channel_apply()
128 u32 arr, val, mask, cfgr, presc = 0; in stm32_pwm_lp_apply() local
189 ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); in stm32_pwm_lp_apply()
202 if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || (arr != prd - 1)) in stm32_pwm_lp_apply()
213 if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || in stm32_pwm_lp_apply()
214 ((FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity) && !priv->num_cc_chans)) { in stm32_pwm_lp_apply()
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| /drivers/irqchip/ |
| A D | irq-gic-v5-irs.c | 67 u32 n, cfgr; in gicv5_irs_init_ist_linear() local
101 cfgr = FIELD_PREP(GICV5_IRS_IST_CFGR_STRUCTURE, in gicv5_irs_init_ist_linear()
107 irs_writel_relaxed(irs_data, cfgr, GICV5_IRS_IST_CFGR); in gicv5_irs_init_ist_linear()
130 u32 cfgr, n; in gicv5_irs_init_ist_two_level() local
150 cfgr = FIELD_PREP(GICV5_IRS_IST_CFGR_STRUCTURE, in gicv5_irs_init_ist_two_level()
155 irs_writel_relaxed(irs_data, cfgr, GICV5_IRS_IST_CFGR); in gicv5_irs_init_ist_two_level()
445 u32 selr, cfgr; in gicv5_spi_irq_set_type() local
475 cfgr = FIELD_PREP(GICV5_IRS_SPI_CFGR_TM, level); in gicv5_spi_irq_set_type()
476 irs_writel_relaxed(irs_data, cfgr, GICV5_IRS_SPI_CFGR); in gicv5_spi_irq_set_type()
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| A D | irq-gic-v5-its.c | 81 FIELD_GET(GICV5_ITS_DT_CFGR_##f, (its)->devtab_cfgr.cfgr)
576 u32 cfgr; in gicv5_its_alloc_devtab_linear() local
600 cfgr = FIELD_PREP(GICV5_ITS_DT_CFGR_STRUCTURE, in gicv5_its_alloc_devtab_linear()
604 its_writel_relaxed(its, cfgr, GICV5_ITS_DT_CFGR); in gicv5_its_alloc_devtab_linear()
609 its->devtab_cfgr.cfgr = cfgr; in gicv5_its_alloc_devtab_linear()
627 u32 cfgr; in gicv5_its_alloc_devtab_two_level() local
665 cfgr = FIELD_PREP(GICV5_ITS_DT_CFGR_STRUCTURE, in gicv5_its_alloc_devtab_two_level()
669 its_writel_relaxed(its, cfgr, GICV5_ITS_DT_CFGR); in gicv5_its_alloc_devtab_two_level()
674 its->devtab_cfgr.cfgr = cfgr; in gicv5_its_alloc_devtab_two_level()
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| /drivers/mmc/host/ |
| A D | mmci_stm32_sdmmc.c | 490 u32 cfgr; in sdmmc_dlyb_mp15_set_cfg() local
494 cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) | in sdmmc_dlyb_mp15_set_cfg()
496 writel_relaxed(cfgr, dlyb->base + DLYB_CFGR); in sdmmc_dlyb_mp15_set_cfg()
507 u32 cfgr; in sdmmc_dlyb_mp15_prepare() local
513 ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr, in sdmmc_dlyb_mp15_prepare()
514 (cfgr & DLYB_CFGR_LNGF), in sdmmc_dlyb_mp15_prepare()
519 i, cfgr); in sdmmc_dlyb_mp15_prepare()
523 lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr); in sdmmc_dlyb_mp15_prepare()
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| /drivers/memory/ |
| A D | stm32-fmc2-ebi.c | 206 u32 cfgr; member
306 u32 cfgr; in stm32_fmc2_ebi_mp25_check_clk_period() local
309 ret = regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); in stm32_fmc2_ebi_mp25_check_clk_period()
313 if (cfgr & FMC2_CFGR_CCLKEN && !ebi->access_granted) in stm32_fmc2_ebi_mp25_check_clk_period()
449 u32 cfgr, btr, clk_period; in stm32_fmc2_ebi_mp25_ns_to_clk_period() local
452 ret = regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); in stm32_fmc2_ebi_mp25_ns_to_clk_period()
456 if (cfgr & FMC2_CFGR_CCLKEN) { in stm32_fmc2_ebi_mp25_ns_to_clk_period()
837 u32 val, cfgr; in stm32_fmc2_ebi_mp25_set_clk_period() local
840 ret = regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); in stm32_fmc2_ebi_mp25_set_clk_period()
844 if (cfgr & FMC2_CFGR_CCLKEN) { in stm32_fmc2_ebi_mp25_set_clk_period()
[all …]
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| /drivers/perf/ |
| A D | arm_smmuv3_pmu.c | 851 u32 cfgr, reg_size; in smmu_pmu_probe() local
884 cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR); in smmu_pmu_probe()
887 if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) { in smmu_pmu_probe()
904 smmu_pmu->num_counters = FIELD_GET(SMMU_PMCG_CFGR_NCTR, cfgr) + 1; in smmu_pmu_probe()
906 smmu_pmu->global_filter = !!(cfgr & SMMU_PMCG_CFGR_SID_FILTER_TYPE); in smmu_pmu_probe()
908 reg_size = FIELD_GET(SMMU_PMCG_CFGR_SIZE, cfgr); in smmu_pmu_probe()
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| /drivers/net/ethernet/freescale/enetc/ |
| A D | enetc_pf.c | 284 u32 cfgr; in enetc_pf_set_vf_spoofchk() local
289 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1)); in enetc_pf_set_vf_spoofchk()
290 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0); in enetc_pf_set_vf_spoofchk()
291 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr); in enetc_pf_set_vf_spoofchk()
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| /drivers/pinctrl/ |
| A D | pinctrl-at91-pio4.c | 145 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK]; member
1013 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] = in atmel_pctrl_suspend()
1036 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]); in atmel_pctrl_resume()
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| /drivers/net/ethernet/freescale/ |
| A D | fec_main.c | 1226 u32 cfgr; in fec_restart() local
1237 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) in fec_restart()
1240 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; in fec_restart()
1241 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); in fec_restart()
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