Searched refs:clear_state_gpu_addr (Results 1 – 13 of 13) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_rlc.h | 283 uint64_t clear_state_gpu_addr; member
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| A D | amdgpu_rlc.c | 139 &adev->gfx.rlc.clear_state_gpu_addr, in amdgpu_gfx_rlc_init_csb()
272 &adev->gfx.rlc.clear_state_gpu_addr, in amdgpu_gfx_rlc_fini()
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| A D | gfx_v6_0.c | 2388 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v6_0_rlc_init()
2398 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; in gfx_v6_0_rlc_init()
2810 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_gfx_cgpg()
2894 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
2902 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
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| A D | gfx_v7_0.c | 3804 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3805 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
4420 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v7_0_sw_fini()
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| A D | gfx_v12_0.c | 723 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v12_0_rlc_fini()
1905 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v12_0_init_csb()
1907 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v12_0_init_csb()
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| A D | gfx_v10_0.c | 4351 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v10_0_rlc_fini()
5454 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v10_0_init_csb()
5456 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v10_0_init_csb()
5460 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v10_0_init_csb()
5462 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v10_0_init_csb()
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| A D | gfx_v8_0.c | 2047 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_sw_fini()
3857 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v8_0_init_csb()
3859 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
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| A D | gfx_v11_0.c | 879 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v11_0_rlc_fini()
2223 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v11_0_init_csb()
2225 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v11_0_init_csb()
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| A D | gfx_v9_0.c | 2476 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v9_0_sw_fini()
2771 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v9_0_init_csb()
2773 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v9_0_init_csb()
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| /drivers/gpu/drm/radeon/ |
| A D | evergreen.c | 4266 &rdev->rlc.clear_state_gpu_addr); in sumo_rlc_init()
4285 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256; in sumo_rlc_init()
4292 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4); in sumo_rlc_init()
4412 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in evergreen_rlc_resume()
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| A D | si.c | 5269 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5766 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5772 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
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| A D | radeon.h | 952 uint64_t clear_state_gpu_addr; member
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| A D | cik.c | 6618 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6619 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
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