| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.h | 33 display_e2e_pipe_params_st *pipes);
37 display_e2e_pipe_params_st *pipes,
41 display_e2e_pipe_params_st *pipes,
46 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
65 enum dc_validate_mode validate_mode, display_e2e_pipe_params_st *pipes);
77 display_e2e_pipe_params_st *pipes,
80 dc_validate_mode, display_e2e_pipe_params_st *pipes);
87 display_e2e_pipe_params_st *pipes);
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| A D | display_rq_dlg_calc_20.h | 64 const display_e2e_pipe_params_st *e2e_pipe_param,
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| A D | display_rq_dlg_calc_20v2.h | 64 const display_e2e_pipe_params_st *e2e_pipe_param,
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| A D | dcn20_fpu.c | 992 display_e2e_pipe_params_st *pipes) in dcn20_populate_dml_writeback_from_context()
1032 display_e2e_pipe_params_st *pipes, in dcn20_fpu_set_wb_arb_params()
1143 display_e2e_pipe_params_st *pipes, in dcn20_calculate_dlg_params()
1317 display_e2e_pipe_params_st *pipes, in dcn20_populate_dml_pipes_from_context()
1732 display_e2e_pipe_params_st *pipes, in dcn20_calculate_wm()
2030 enum dc_validate_mode validate_mode, display_e2e_pipe_params_st *pipes) in dcn20_validate_bandwidth_internal()
2080 enum dc_validate_mode validate_mode, display_e2e_pipe_params_st *pipes) in dcn20_validate_bandwidth_fp()
2157 display_e2e_pipe_params_st *pipes, in dcn21_populate_dml_pipes_from_context()
2210 display_e2e_pipe_params_st *pipes, in calculate_wm_set_for_vlevel()
2237 display_e2e_pipe_params_st *pipes, in dcn21_calculate_wm()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.h | 36 display_e2e_pipe_params_st *pipes,
43 display_e2e_pipe_params_st *pipes,
49 display_e2e_pipe_params_st *pipes,
55 display_e2e_pipe_params_st *pipes,
63 display_e2e_pipe_params_st *pipes,
69 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
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| A D | display_rq_dlg_calc_32.h | 46 const display_e2e_pipe_params_st *e2e_pipe_param,
66 display_e2e_pipe_params_st *e2e_pipe_param,
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| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.h | 51 display_e2e_pipe_params_st *pipes,
64 display_e2e_pipe_params_st *pipes,
71 display_e2e_pipe_params_st *pipes,
76 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
80 display_e2e_pipe_params_st *pipes,
106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | dcn30_fpu.h | 33 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
37 display_e2e_pipe_params_st *pipes,
45 display_e2e_pipe_params_st *pipes,
65 display_e2e_pipe_params_st *pipes,
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| A D | display_rq_dlg_calc_30.h | 60 const display_e2e_pipe_params_st *e2e_pipe_param,
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| A D | dcn30_fpu.c | 182 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) in dcn30_fpu_populate_dml_writeback_from_context()
273 display_e2e_pipe_params_st *pipes, in dcn30_fpu_set_mcif_arb_params()
305 display_e2e_pipe_params_st *pipes, in dcn30_fpu_calculate_wm_and_dlg()
622 display_e2e_pipe_params_st *pipes, in dcn30_find_dummy_latency_index_for_fw_based_mclk_switch()
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_lib.h | 55 const display_e2e_pipe_params_st *e2e_pipe_param,
73 display_e2e_pipe_params_st *e2e_pipe_param,
78 const display_e2e_pipe_params_st *e2e_pipe_param,
105 display_e2e_pipe_params_st *pipes,
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| A D | display_mode_vba.h | 34 …tr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, …
75 …tr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, …
150 const display_e2e_pipe_params_st *pipes,
154 const display_e2e_pipe_params_st *pipes,
158 const display_e2e_pipe_params_st *pipes,
162 const display_e2e_pipe_params_st *pipes,
167 const display_e2e_pipe_params_st *pipes,
171 const display_e2e_pipe_params_st *pipes,
587 display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
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| A D | display_mode_vba.c | 46 const display_e2e_pipe_params_st *pipes,
54 const display_e2e_pipe_params_st *pipes, in dml_get_voltage_level()
61 sizeof(display_e2e_pipe_params_st) * num_pipes) != 0; in dml_get_voltage_level()
209 const display_e2e_pipe_params_st *pipes, in get_total_immediate_flip_bytes()
218 const display_e2e_pipe_params_st *pipes, in get_total_immediate_flip_bw()
231 const display_e2e_pipe_params_st *pipes, in get_total_prefetch_bw()
245 const display_e2e_pipe_params_st *pipes, in get_total_surface_size_in_mall_bytes()
292 bool get_is_phantom_pipe(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, in get_is_phantom_pipe()
517 display_e2e_pipe_params_st *pipes = mode_lib->vba.cache_pipes; in fetch_pipe_params()
959 const display_e2e_pipe_params_st *pipes, in recalculate_params()
[all …]
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| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.h | 45 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
55 display_e2e_pipe_params_st *pipes);
59 display_e2e_pipe_params_st *pipes,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | dcn31_fpu.h | 35 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
43 display_e2e_pipe_params_st *pipes,
57 display_e2e_pipe_params_st *pipes,
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| A D | display_rq_dlg_calc_31.h | 60 const display_e2e_pipe_params_st *e2e_pipe_param,
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 90 display_e2e_pipe_params_st *pipes,
111 display_e2e_pipe_params_st *pipes,
180 display_e2e_pipe_params_st *pipes);
185 display_e2e_pipe_params_st *pipes,
211 display_e2e_pipe_params_st *pipes,
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| /drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.h | 120 display_e2e_pipe_params_st *pipes,
157 display_e2e_pipe_params_st *pipes,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | dcn314_fpu.h | 37 display_e2e_pipe_params_st *pipes,
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| A D | display_rq_dlg_calc_314.h | 61 const display_e2e_pipe_params_st *e2e_pipe_param,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| A D | dcn351_fpu.h | 14 display_e2e_pipe_params_st *pipes,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| A D | dcn35_fpu.h | 39 display_e2e_pipe_params_st *pipes,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.h | 38 display_e2e_pipe_params_st *pipes,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.h | 64 const display_e2e_pipe_params_st *e2e_pipe_param,
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| /drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.h | 50 display_e2e_pipe_params_st *pipes,
|