Searched refs:dml_input (Results 1 – 5 of 5) sorted by relevance
299 ….soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; in dcn30_fpu_update_soc_for_wm_a()516 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn30_fpu_calculate_wm_and_dlg()670 base->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn3_fpu_build_wm_range_table()671 base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn3_fpu_build_wm_range_table()672 …base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_ex… in dcn3_fpu_build_wm_range_table()692 base->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 0; in dcn3_fpu_build_wm_range_table()693 base->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn3_fpu_build_wm_range_table()694 …base->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_ex… in dcn3_fpu_build_wm_range_table()711 base->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = pstate_latency_us; in dcn3_fpu_build_wm_range_table()712 base->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2; in dcn3_fpu_build_wm_range_table()[all …]
212 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn32_build_wm_range_table_fpu()214 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn32_build_wm_range_table_fpu()224 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us; in dcn32_build_wm_range_table_fpu()226 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn32_build_wm_range_table_fpu()237 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50; in dcn32_build_wm_range_table_fpu()239 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn32_build_wm_range_table_fpu()260 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2… in dcn32_build_wm_range_table_fpu()2347 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()2385 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()2626 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()[all …]
173 } dml_input; member
479 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; member
464 struct _vcs_dpi_display_e2e_pipe_params_st *input = &pipe->dml_input; in dcn_bw_calc_rq_dlg_ttu()
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