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Searched refs:ethtype (Results 1 – 25 of 26) sorted by relevance

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/drivers/net/ethernet/qlogic/qed/
A Dqed_dcbx.c85 bool ethtype; in qed_dcbx_default_tlv() local
90 ethtype = qed_dcbx_app_ethtype(app_info_bitmap); in qed_dcbx_default_tlv()
110 bool ethtype; in qed_dcbx_fcoe_tlv() local
115 ethtype = qed_dcbx_app_ethtype(app_info_bitmap); in qed_dcbx_fcoe_tlv()
122 bool ethtype; in qed_dcbx_roce_tlv() local
1149 if (p_params->app_entry[i].ethtype) in qed_dcbx_set_app_data()
1730 bool ethtype; in qed_dcbnl_getapp() local
1741 if ((entry->ethtype == ethtype) && (entry->proto_id == idval)) { in qed_dcbnl_getapp()
1765 bool ethtype; in qed_dcbnl_setapp() local
1776 if ((entry->ethtype == ethtype) && (entry->proto_id == idval)) in qed_dcbnl_setapp()
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/drivers/net/dsa/microchip/
A Dksz9477_tc_flower.c38 u16 ethtype = 0; in ksz9477_flower_parse_key_l2() local
52 ethtype = be16_to_cpu(match.key->n_proto); in ksz9477_flower_parse_key_l2()
84 ksz9477_acl_match_process_l2(dev, port, ethtype, src_mac, dst_mac, in ksz9477_flower_parse_key_l2()
A Dksz9477_acl.c1401 u16 ethtype, u8 *src_mac, u8 *dst_mac, in ksz9477_acl_match_process_l2() argument
1412 ksz9477_acl_matching_rule_cfg_l2(entry->entry, ethtype, src_mac, in ksz9477_acl_match_process_l2()
1430 ksz9477_acl_matching_rule_cfg_l2(entry->entry, ethtype, mac, in ksz9477_acl_match_process_l2()
A Dksz9477.h97 u16 ethtype, u8 *src_mac, u8 *dst_mac,
/drivers/net/ethernet/chelsio/cxgb4/
A Dcxgb4_tc_flower.c195 fs->val.ethtype = ethtype_key; in cxgb4_process_flow_match()
196 fs->mask.ethtype = ethtype_mask; in cxgb4_process_flow_match()
295 if (fs->val.ethtype == ETH_P_8021Q) { in cxgb4_process_flow_match()
296 fs->val.ethtype = 0; in cxgb4_process_flow_match()
297 fs->mask.ethtype = 0; in cxgb4_process_flow_match()
A Dcxgb4_filter.c262 unsupported(fconf, ETHERTYPE_F, fs->val.ethtype, in validate_filter()
263 fs->mask.ethtype) || in validate_filter()
874 fwr->ethtype = htons(f->fs.val.ethtype); in set_filter_wr()
875 fwr->ethtypem = htons(f->fs.mask.ethtype); in set_filter_wr()
1070 if (fs->val.ethtype && !fs->mask.ethtype) in fill_default_mask()
1071 fs->mask.ethtype |= ~0; in fill_default_mask()
1219 ntuple_mask |= (u64)fs->mask.ethtype << tp->ethertype_shift; in is_filter_exact_match()
1281 if (tp->ethertype_shift >= 0 && fs->mask.ethtype) in hash_filter_ntuple()
1282 ntuple |= (u64)(fs->val.ethtype) << tp->ethertype_shift; in hash_filter_ntuple()
A Dt4fw_api.h182 __be16 ethtype; member
214 __be16 ethtype; member
800 __be16 ethtype;
A Dcxgb4.h1339 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ member
/drivers/infiniband/hw/usnic/
A Dusnic_fwd.h101 filter->u.usnic.ethtype = ETH_P_IBOE; in usnic_fwd_init_usnic_filter()
/drivers/net/ethernet/netronome/nfp/flower/
A Dcmsg.h246 __be16 ethtype; member
252 __be16 ethtype; member
A Daction.c57 push_mpls->ethtype = act->mpls_push.proto; in nfp_fl_push_mpls()
71 pop_mpls->ethtype = act->mpls_pop.proto; in nfp_fl_pop_mpls()
/drivers/net/ethernet/mellanox/mlx5/core/
A Dfs_cmd.c617 MLX5_SET(vlan, vlan, ethtype, fte->act_dests.action.vlan[0].ethtype); in mlx5_cmd_set_fte()
623 MLX5_SET(vlan, vlan, ethtype, fte->act_dests.action.vlan[1].ethtype); in mlx5_cmd_set_fte()
A Dfs_core.c1917 return vlan0->ethtype != vlan1->ethtype || in check_conflicting_actions_vlan()
A Deswitch_offloads.c689 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]); in mlx5_eswitch_add_offloaded_rule()
693 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]); in mlx5_eswitch_add_offloaded_rule()
/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/
A Ddr_cmd.c854 MLX5_SET(vlan, vlan, ethtype, fte->action.vlan[0].ethtype); in mlx5dr_cmd_set_fte()
860 MLX5_SET(vlan, vlan, ethtype, fte->action.vlan[1].ethtype); in mlx5dr_cmd_set_fte()
A Dfs_dr.c231 u16 n_ethtype = vlan->ethtype; in create_action_push_vlan()
/drivers/net/ethernet/mellanox/mlxsw/
A Dspectrum.h693 int mlxsw_sp_ethtype_to_sver_type(u16 ethtype, u8 *p_sver_type);
695 u16 ethtype);
697 u16 ethtype);
A Dspectrum.c368 int mlxsw_sp_ethtype_to_sver_type(u16 ethtype, u8 *p_sver_type) in mlxsw_sp_ethtype_to_sver_type() argument
370 switch (ethtype) { in mlxsw_sp_ethtype_to_sver_type()
385 u16 ethtype) in mlxsw_sp_port_egress_ethtype_set() argument
392 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type); in mlxsw_sp_port_egress_ethtype_set()
401 u16 vid, u16 ethtype) in __mlxsw_sp_port_pvid_set() argument
408 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type); in __mlxsw_sp_port_pvid_set()
429 u16 ethtype) in mlxsw_sp_port_pvid_set() argument
438 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid, ethtype); in mlxsw_sp_port_pvid_set()
450 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid, ethtype); in mlxsw_sp_port_pvid_set()
/drivers/net/ethernet/cisco/enic/
A Dvnic_devcmd.h583 u16 ethtype; member
/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/
A Dingress_lgcy.c225 flow_act.vlan[0].ethtype = ETH_P_8021Q; in esw_acl_ingress_lgcy_setup()
A Dingress_ofld.c42 flow_act.vlan[0].ethtype = ETH_P_8021Q; in esw_acl_ingress_prio_tag_create()
/drivers/net/ethernet/intel/i40e/
A Di40e_prototype.h388 u8 *mac_addr, u16 ethtype, u16 flags,
A Di40e_common.c3717 u8 *mac_addr, u16 ethtype, u16 flags, in i40e_aq_add_rem_control_packet_filter() argument
3744 cmd->etype = cpu_to_le16(ethtype); in i40e_aq_add_rem_control_packet_filter()
3772 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; in i40e_add_filter_to_drop_tx_flow_control_frames() local
3775 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, in i40e_add_filter_to_drop_tx_flow_control_frames()
/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
A Dfs_hws.c590 u16 n_ethtype = vlan->ethtype; in mlx5_fs_calc_vlan_hdr()
/drivers/net/ethernet/broadcom/
A Dtg3.c18031 char *ethtype; in tg3_init_one() local
18034 ethtype = "10/100Base-TX"; in tg3_init_one()
18036 ethtype = "1000Base-SX"; in tg3_init_one()
18038 ethtype = "10/100/1000Base-T"; in tg3_init_one()
18042 tg3_phy_string(tp), ethtype, in tg3_init_one()

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