Home
last modified time | relevance | path

Searched refs:final_offset (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/display/
A Ddrm_dsc_helper.c210 pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset); in drm_dsc_pps_payload_pack()
1372 vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - in drm_dsc_compute_rc_parameters()
1376 if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { in drm_dsc_compute_rc_parameters()
1382 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); in drm_dsc_compute_rc_parameters()
1411 (vdsc_cfg->final_offset * (1 << 11)) / in drm_dsc_compute_rc_parameters()
1500 cfg->initial_offset, cfg->final_offset, cfg->slice_bpg_offset); in drm_dsc_dump_config_main_params()
/drivers/gpu/drm/amd/display/dc/dsc/
A Drc_calc_dpi.c64 to->final_offset = from->final_offset; in copy_pps_fields()
/drivers/gpu/drm/i915/display/
A Dintel_vdsc_regs.h155 #define DSC_PPS8_FINAL_OFFSET(final_offset) REG_FIELD_PREP(DSC_PPS8_FINAL_OFFSET_MASK, \ argument
156 final_offset)
A Dintel_vdsc.c527 pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) | in intel_dsc_pps_configure()
948 vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
A Dintel_display.c5407 PIPE_CONF_CHECK_I(dsc.config.final_offset); in intel_pipe_config_compare()
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_dsc.c108 data |= dsc->final_offset; in dpu_hw_dsc_config()
A Ddpu_hw_dsc_1_2.c194 ((dsc->final_offset & 0xffff) << 16); in dpu_hw_dsc_config_1_2()
/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
A Ddcn20_dsc.c309 DC_LOG_DSC("\tfinal_offset %d", pps->final_offset); in dsc_log_pps()
549 reg_vals->pps.final_offset = 0; in dsc_init_reg_values()
672 FINAL_OFFSET, reg_vals->pps.final_offset); in dsc_write_to_registers()
/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.c294 FINAL_OFFSET, reg_vals->pps.final_offset); in dsc_write_to_registers()

Completed in 31 milliseconds