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Searched refs:gfx_table (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Daldebaran_ppt.c361 dpm_table = &dpm_context->dpm_tables.gfx_table; in aldebaran_get_dpm_ultimate_freq()
424 dpm_table = &dpm_context->dpm_tables.gfx_table; in aldebaran_set_default_dpm_table()
596 struct smu_13_0_dpm_table *gfx_table = in aldebaran_populate_umd_state_clk() local
597 &dpm_context->dpm_tables.gfx_table; in aldebaran_populate_umd_state_clk()
605 pstate_table->gfxclk_pstate.min = gfx_table->min; in aldebaran_populate_umd_state_clk()
606 pstate_table->gfxclk_pstate.peak = gfx_table->max; in aldebaran_populate_umd_state_clk()
1325 struct smu_13_0_dpm_table *gfx_table = in aldebaran_set_performance_level() local
1326 &dpm_context->dpm_tables.gfx_table; in aldebaran_set_performance_level()
1403 (max > dpm_context->dpm_tables.gfx_table.max)) { in aldebaran_set_soft_freq_limited_range()
1410 min_clk = dpm_context->dpm_tables.gfx_table.min; in aldebaran_set_soft_freq_limited_range()
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A Dsmu_v13_0_6_ppt.c901 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v13_0_6_get_dpm_ultimate_freq()
1026 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v13_0_6_set_default_dpm_table()
1106 struct smu_13_0_dpm_table *gfx_table = in smu_v13_0_6_populate_umd_state_clk() local
1107 &dpm_context->dpm_tables.gfx_table; in smu_v13_0_6_populate_umd_state_clk()
1114 pstate_table->gfxclk_pstate.min = gfx_table->min; in smu_v13_0_6_populate_umd_state_clk()
1963 struct smu_13_0_dpm_table *gfx_table = in smu_v13_0_6_set_performance_level() local
1964 &dpm_context->dpm_tables.gfx_table; in smu_v13_0_6_set_performance_level()
1985 smu, gfx_table->min, gfx_table->max); in smu_v13_0_6_set_performance_level()
2082 min_clk = dpm_context->dpm_tables.gfx_table.min; in smu_v13_0_6_set_soft_freq_limited_range()
2134 dpm_context->dpm_tables.gfx_table.min); in smu_v13_0_6_usr_edit_dpm_table()
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A Daldebaran_ppt.h61 struct aldebaran_single_dpm_table gfx_table; member
A Dsmu_v13_0_7_ppt.c601 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v13_0_7_set_default_dpm_table()
879 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v13_0_7_get_dpm_ultimate_freq()
1200 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); in smu_v13_0_7_print_clk_levels()
1991 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); in smu_v13_0_7_force_clk_levels()
2291 struct smu_13_0_dpm_table *gfx_table = in smu_v13_0_7_populate_umd_state_clk() local
2292 &dpm_context->dpm_tables.gfx_table; in smu_v13_0_7_populate_umd_state_clk()
2310 pstate_table->gfxclk_pstate.min = gfx_table->min; in smu_v13_0_7_populate_umd_state_clk()
2312 (driver_clocks.GameClockAc < gfx_table->max)) in smu_v13_0_7_populate_umd_state_clk()
2315 pstate_table->gfxclk_pstate.peak = gfx_table->max; in smu_v13_0_7_populate_umd_state_clk()
2333 driver_clocks.BaseClockAc < gfx_table->max) in smu_v13_0_7_populate_umd_state_clk()
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A Dsmu_v13_0_0_ppt.c594 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v13_0_0_set_default_dpm_table()
890 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v13_0_0_get_dpm_ultimate_freq()
1211 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); in smu_v13_0_0_print_clk_levels()
2002 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); in smu_v13_0_0_force_clk_levels()
2305 struct smu_13_0_dpm_table *gfx_table = in smu_v13_0_0_populate_umd_state_clk() local
2306 &dpm_context->dpm_tables.gfx_table; in smu_v13_0_0_populate_umd_state_clk()
2324 pstate_table->gfxclk_pstate.min = gfx_table->min; in smu_v13_0_0_populate_umd_state_clk()
2326 (driver_clocks.GameClockAc < gfx_table->max)) in smu_v13_0_0_populate_umd_state_clk()
2329 pstate_table->gfxclk_pstate.peak = gfx_table->max; in smu_v13_0_0_populate_umd_state_clk()
2347 driver_clocks.BaseClockAc < gfx_table->max) in smu_v13_0_0_populate_umd_state_clk()
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A Dsmu_v13_0.c1587 struct smu_13_0_dpm_table *gfx_table = in smu_v13_0_set_performance_level() local
1588 &dpm_context->dpm_tables.gfx_table; in smu_v13_0_set_performance_level()
1613 sclk_min = sclk_max = gfx_table->max; in smu_v13_0_set_performance_level()
1621 sclk_min = sclk_max = gfx_table->min; in smu_v13_0_set_performance_level()
1629 sclk_min = gfx_table->min; in smu_v13_0_set_performance_level()
1630 sclk_max = gfx_table->max; in smu_v13_0_set_performance_level()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega20_hwmgr.c600 dpm_table = &(data->dpm_table.gfx_table); in vega20_setup_gfxclk_dpm_table()
666 dpm_table = &(data->dpm_table.gfx_table); in vega20_setup_default_dpm_tables()
1481 &(data->dpm_table.gfx_table); in vega20_get_sclk_od()
1483 &(data->golden_dpm_table.gfx_table); in vega20_get_sclk_od()
1500 &(data->golden_dpm_table.gfx_table); in vega20_set_sclk_od()
1571 struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table); in vega20_populate_umdpstate_clocks() local
1583 hwmgr->pstate_sclk_peak = gfx_table->dpm_levels[gfx_table->count - 1].value; in vega20_populate_umdpstate_clocks()
2400 data->dpm_table.gfx_table.dpm_state.soft_min_level = in vega20_force_dpm_highest()
2442 data->dpm_table.gfx_table.dpm_state.soft_min_level = in vega20_force_dpm_lowest()
2581 data->dpm_table.gfx_table.count - 1); in vega20_force_clock_level()
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A Dvega12_hwmgr.c667 dpm_table = &(data->dpm_table.gfx_table); in vega12_setup_default_dpm_tables()
1663 data->dpm_table.gfx_table.dpm_state.soft_min_level = in vega12_force_dpm_highest()
1664 data->dpm_table.gfx_table.dpm_state.soft_max_level = in vega12_force_dpm_highest()
1692 data->dpm_table.gfx_table.dpm_state.soft_min_level = in vega12_force_dpm_lowest()
1693 data->dpm_table.gfx_table.dpm_state.soft_max_level = in vega12_force_dpm_lowest()
1866 dpm_table = &(data->dpm_table.gfx_table); in vega12_get_sclks()
2037 data->dpm_table.gfx_table.dpm_state.soft_min_level = in vega12_force_clock_level()
2372 dpm_table = &(data->dpm_table.gfx_table); in vega12_apply_clocks_adjust_rules()
2673 for (i = 0; i < dpm_table->gfx_table.count; i++) {
2674 if (dpm_table->gfx_table.dpm_levels[i].enabled &&
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A Dvega10_hwmgr.c1361 dpm_table = &(data->dpm_table.gfx_table); in vega10_setup_default_dpm_tables()
3579 &(data->dpm_table.gfx_table), in vega10_trim_dpm_states()
3649 data->dpm_table.gfx_table.dpm_state.soft_min_level) { in vega10_upload_dpm_bootup_level()
3655 data->dpm_table.gfx_table.dpm_state.soft_min_level = in vega10_upload_dpm_bootup_level()
3707 data->dpm_table.gfx_table.dpm_state.soft_max_level) { in vega10_upload_dpm_max_level()
3712 data->dpm_table.gfx_table.dpm_state.soft_max_level = in vega10_upload_dpm_max_level()
5153 &(data->golden_dpm_table.gfx_table); in vega10_get_sclk_od()
5168 &(data->golden_dpm_table.gfx_table); in vega10_set_sclk_od()
5433 golden_table = &(data->golden_dpm_table.gfx_table); in vega10_check_clk_voltage_valid()
5463 &data->dpm_table.gfx_table; in vega10_odn_update_power_state()
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A Dvega10_hwmgr.h148 struct vega10_single_dpm_table gfx_table; member
A Dvega12_hwmgr.h126 struct vega12_single_dpm_table gfx_table; member
A Dvega20_hwmgr.h179 struct vega20_single_dpm_table gfx_table; member
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Darcturus_ppt.c387 dpm_table = &dpm_context->dpm_tables.gfx_table; in arcturus_set_default_dpm_table()
575 struct smu_11_0_dpm_table *gfx_table = in arcturus_populate_umd_state_clk() local
576 &dpm_context->dpm_tables.gfx_table; in arcturus_populate_umd_state_clk()
584 pstate_table->gfxclk_pstate.min = gfx_table->min; in arcturus_populate_umd_state_clk()
585 pstate_table->gfxclk_pstate.peak = gfx_table->max; in arcturus_populate_umd_state_clk()
593 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL && in arcturus_populate_umd_state_clk()
597 gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value; in arcturus_populate_umd_state_clk()
829 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); in arcturus_emit_clk_levels()
959 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; in arcturus_upload_dpm_level()
1022 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); in arcturus_force_clk_levels()
A Darcturus_ppt.h61 struct arcturus_single_dpm_table gfx_table; member
A Dsmu_v11_0.c1857 struct smu_11_0_dpm_table *gfx_table = in smu_v11_0_set_performance_level() local
1858 &dpm_context->dpm_tables.gfx_table; in smu_v11_0_set_performance_level()
1874 sclk_min = sclk_max = gfx_table->max; in smu_v11_0_set_performance_level()
1879 sclk_min = sclk_max = gfx_table->min; in smu_v11_0_set_performance_level()
1884 sclk_min = gfx_table->min; in smu_v11_0_set_performance_level()
1885 sclk_max = gfx_table->max; in smu_v11_0_set_performance_level()
A Dnavi10_ppt.c992 dpm_table = &dpm_context->dpm_tables.gfx_table; in navi10_set_default_dpm_table()
1713 struct smu_11_0_dpm_table *gfx_table = in navi10_populate_umd_state_clk() local
1714 &dpm_context->dpm_tables.gfx_table; in navi10_populate_umd_state_clk()
1724 pstate_table->gfxclk_pstate.min = gfx_table->min; in navi10_populate_umd_state_clk()
1768 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value; in navi10_populate_umd_state_clk()
1779 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK && in navi10_populate_umd_state_clk()
A Dsienna_cichlid_ppt.c982 dpm_table = &dpm_context->dpm_tables.gfx_table; in sienna_cichlid_set_default_dpm_table()
1489 struct smu_11_0_dpm_table *gfx_table = in sienna_cichlid_populate_umd_state_clk() local
1490 &dpm_context->dpm_tables.gfx_table; in sienna_cichlid_populate_umd_state_clk()
1499 pstate_table->gfxclk_pstate.min = gfx_table->min; in sienna_cichlid_populate_umd_state_clk()
1500 pstate_table->gfxclk_pstate.peak = gfx_table->max; in sienna_cichlid_populate_umd_state_clk()
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0_2_ppt.c524 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v14_0_2_set_default_dpm_table()
808 dpm_table = &dpm_context->dpm_tables.gfx_table; in smu_v14_0_2_get_dpm_ultimate_freq()
1072 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); in smu_v14_0_2_print_clk_levels()
1397 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); in smu_v14_0_2_force_clk_levels()
1585 struct smu_14_0_dpm_table *gfx_table = in smu_v14_0_2_populate_umd_state_clk() local
1586 &dpm_context->dpm_tables.gfx_table; in smu_v14_0_2_populate_umd_state_clk()
1604 pstate_table->gfxclk_pstate.min = gfx_table->min; in smu_v14_0_2_populate_umd_state_clk()
1606 (driver_clocks.GameClockAc < gfx_table->max)) in smu_v14_0_2_populate_umd_state_clk()
1609 pstate_table->gfxclk_pstate.peak = gfx_table->max; in smu_v14_0_2_populate_umd_state_clk()
1627 driver_clocks.BaseClockAc < gfx_table->max) in smu_v14_0_2_populate_umd_state_clk()
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A Dsmu_v14_0.c1250 struct smu_14_0_dpm_table *gfx_table = in smu_v14_0_set_performance_level() local
1251 &dpm_context->dpm_tables.gfx_table; in smu_v14_0_set_performance_level()
1276 sclk_min = sclk_max = gfx_table->max; in smu_v14_0_set_performance_level()
1284 sclk_min = sclk_max = gfx_table->min; in smu_v14_0_set_performance_level()
1292 sclk_min = gfx_table->min; in smu_v14_0_set_performance_level()
1293 sclk_max = gfx_table->max; in smu_v14_0_set_performance_level()
/drivers/gpu/drm/amd/pm/swsmu/inc/
A Dsmu_v14_0.h92 struct smu_14_0_dpm_table gfx_table; member
A Dsmu_v11_0.h103 struct smu_11_0_dpm_table gfx_table; member
A Dsmu_v13_0.h97 struct smu_13_0_dpm_table gfx_table; member

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