Searched refs:init_cmd (Results 1 – 3 of 3) sorted by relevance
| /drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ |
| A D | fwsec.c | 62 u32 init_cmd; member
89 nvkm_gsp_fwsec_patch(struct nvkm_gsp *gsp, struct nvkm_falcon_fw *fw, u32 if_offset, u32 init_cmd) in nvkm_gsp_fwsec_patch() argument
107 dmemmap->v3.init_cmd = init_cmd; in nvkm_gsp_fwsec_patch()
117 if (init_cmd == NVFW_FALCON_APPIF_DMEMMAPPER_CMD_FRTS) { in nvkm_gsp_fwsec_patch()
173 const struct nvkm_falcon_ucode_desc_v2 *desc, u32 size, u32 init_cmd, in nvkm_gsp_fwsec_v2() argument
218 return nvkm_gsp_fwsec_patch(gsp, fw, desc->InterfaceOffset, init_cmd); in nvkm_gsp_fwsec_v2()
223 const struct nvkm_falcon_ucode_desc_v3 *desc, u32 size, u32 init_cmd, in nvkm_gsp_fwsec_v3() argument
257 return nvkm_gsp_fwsec_patch(gsp, fw, desc->InterfaceOffset, init_cmd); in nvkm_gsp_fwsec_v3()
261 nvkm_gsp_fwsec(struct nvkm_gsp *gsp, const char *name, u32 init_cmd) in nvkm_gsp_fwsec() argument
293 case 2: ret = nvkm_gsp_fwsec_v2(gsp, name, &desc->v2, size, init_cmd, &fw); break; in nvkm_gsp_fwsec()
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| /drivers/thermal/mediatek/ |
| A D | lvts_thermal.c | 129 const u32 *init_cmd; member
1016 lvts_write_config(lvts_ctrl, lvts_data->init_cmd, lvts_data->num_init_cmd); in lvts_ctrl_initialize()
1759 .init_cmd = mt7988_init_cmds,
1771 .init_cmd = default_init_cmds,
1784 .init_cmd = default_init_cmds,
1797 .init_cmd = default_init_cmds,
1810 .init_cmd = default_init_cmds,
1823 .init_cmd = default_init_cmds,
1836 .init_cmd = default_init_cmds,
1849 .init_cmd = default_init_cmds,
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| /drivers/gpu/nova-core/firmware/ |
| A D | fwsec.rs | 65 init_cmd: u32, field
307 dmem_mapper.init_cmd = match cmd { in new_fwsec()
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