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Searched refs:initial_state (Results 1 – 17 of 17) sorted by relevance

/drivers/i2c/muxes/
A Di2c-mux-gpio.c134 unsigned int initial_state; in i2c_mux_gpio_probe() local
178 initial_state = mux->data.idle; in i2c_mux_gpio_probe()
181 initial_state = mux->data.values[0]; in i2c_mux_gpio_probe()
190 if (initial_state & BIT(i)) in i2c_mux_gpio_probe()
/drivers/gpu/drm/radeon/
A Drv730_dpm.c320 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); in rv730_populate_smc_initial_state() local
340 cpu_to_be32(initial_state->low.mclk); in rv730_populate_smc_initial_state()
354 cpu_to_be32(initial_state->low.sclk); in rv730_populate_smc_initial_state()
359 rv770_get_seq_value(rdev, &initial_state->low); in rv730_populate_smc_initial_state()
362 initial_state->low.vddc, in rv730_populate_smc_initial_state()
377 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in rv730_populate_smc_initial_state()
A Dcypress_dpm.c1241 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_initial_state); in cypress_populate_smc_initial_state() local
1265 cpu_to_be32(initial_state->low.mclk); in cypress_populate_smc_initial_state()
1279 cpu_to_be32(initial_state->low.sclk); in cypress_populate_smc_initial_state()
1287 initial_state->low.vddc, in cypress_populate_smc_initial_state()
1293 initial_state->low.vddci, in cypress_populate_smc_initial_state()
1309 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in cypress_populate_smc_initial_state()
1317 initial_state->low.mclk); in cypress_populate_smc_initial_state()
1319 if (initial_state->low.mclk > pi->mclk_edc_enable_threshold) in cypress_populate_smc_initial_state()
A Drv770_dpm.c1028 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); in rv770_populate_smc_initial_state() local
1051 cpu_to_be32(initial_state->low.mclk); in rv770_populate_smc_initial_state()
1065 cpu_to_be32(initial_state->low.sclk); in rv770_populate_smc_initial_state()
1070 rv770_get_seq_value(rdev, &initial_state->low); in rv770_populate_smc_initial_state()
1073 initial_state->low.vddc, in rv770_populate_smc_initial_state()
1087 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in rv770_populate_smc_initial_state()
1094 if (initial_state->low.mclk <= pi->mclk_strobe_mode_threshold) in rv770_populate_smc_initial_state()
1096 rv740_get_mclk_frequency_ratio(initial_state->low.mclk) | 0x10; in rv770_populate_smc_initial_state()
1100 if (initial_state->low.mclk >= pi->mclk_edc_enable_threshold) in rv770_populate_smc_initial_state()
A Dni_dpm.c1683 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); in ni_populate_smc_initial_state() local
1707 cpu_to_be32(initial_state->performance_levels[0].mclk); in ni_populate_smc_initial_state()
1722 cpu_to_be32(initial_state->performance_levels[0].sclk); in ni_populate_smc_initial_state()
1729 initial_state->performance_levels[0].vddc, in ni_populate_smc_initial_state()
1746 initial_state->performance_levels[0].vddci, in ni_populate_smc_initial_state()
1764 initial_state->performance_levels[0].mclk); in ni_populate_smc_initial_state()
1766 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in ni_populate_smc_initial_state()
A Dsi_dpm.c4305 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); in si_populate_smc_initial_state() local
4332 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4348 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state()
4356 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4374 initial_state->performance_levels[0].vddci, in si_populate_smc_initial_state()
4380 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4381 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state()
4382 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4397 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4399 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
/drivers/video/fbdev/riva/
A Drivafb.h51 struct riva_regs initial_state; /* initial startup video mode */ member
A Dfbdev.c1041 riva_save_state(par, &par->initial_state); in rivafb_open()
1061 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext); in rivafb_release()
1062 riva_load_state(par, &par->initial_state); in rivafb_release()
/drivers/scsi/isci/
A Disci.h528 u32 initial_state);
A Dhost.c148 const struct sci_base_state *state_table, u32 initial_state) in sci_init_sm() argument
152 sm->initial_state_id = initial_state; in sci_init_sm()
153 sm->previous_state_id = initial_state; in sci_init_sm()
154 sm->current_state_id = initial_state; in sci_init_sm()
157 handler = sm->state_table[initial_state].enter_state; in sci_init_sm()
/drivers/video/fbdev/nvidia/
A Dnv_type.h99 RIVA_HW_STATE initial_state; member
A Dnvidia.c1000 nvidia_save_vga(par, &par->initial_state); in nvidiafb_open()
1018 nvidia_write_regs(par, &par->initial_state); in nvidiafb_release()
/drivers/nvdimm/
A Dbtt.c627 bool idx_set = false, initial_state = true; in log_set_indices() local
691 initial_state = false; in log_set_indices()
695 if (!initial_state && !idx_set) in log_set_indices()
702 if (initial_state) in log_set_indices()
/drivers/gpu/drm/amd/pm/legacy-dpm/
A Dsi_dpm.c4849 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state); in si_populate_smc_initial_state() local
4876 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4892 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state()
4900 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4918 initial_state->performance_levels[0].vddci, in si_populate_smc_initial_state()
4924 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4925 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state()
4926 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4939 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4941 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
/drivers/regulator/
A Dof_regulator.c327 constraints->initial_state = PM_SUSPEND_MEM; in of_get_regulation_constraints()
A Dcore.c1105 rdev->constraints->initial_state); in suspend_set_initial_state()
1452 if (rdev->constraints->initial_state) { in set_machine_constraints()
/drivers/gpu/drm/amd/display/dc/core/
A Ddc.c4657 struct dc_state *initial_state, in is_pipe_topology_transition_seamless_with_intermediate_step() argument
4661 return dc->hwss.is_pipe_topology_transition_seamless(dc, initial_state, in is_pipe_topology_transition_seamless_with_intermediate_step()

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