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Searched refs:input_width (Results 1 – 11 of 11) sorted by relevance

/drivers/staging/media/atomisp/pci/
A Dsh_css_defs.h204 #define _ISP_SCTBL_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ argument
205 (ISP_BQ_GRID_WIDTH(input_width, deci_factor_log2) + 1)
208 #define _ISP_SCTBL_ALIGNED_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ argument
209 CEIL_MUL(_ISP_SCTBL_WIDTH_PER_COLOR(input_width, deci_factor_log2), \
220 #define _ISP2401_SCTBL_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ argument
221 (ISP_BQ_GRID_WIDTH(input_width, deci_factor_log2) + \
230 #define _ISP_SCTBL_LEGACY_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ argument
231 (ISP_BQ_GRID_WIDTH(input_width, deci_factor_log2) + SH_CSS_SCTBL_LAST_GRID_COUNT)
A Dsh_css_param_shading.c232 unsigned int input_width, input_height, table_width, table_height, i; in prepare_shading_table() local
254 input_width = binary->in_frame_info.res.width; in prepare_shading_table()
276 input_width <<= sensor_binning; in prepare_shading_table()
291 input_width = min(input_width, in_table->sensor_width); in prepare_shading_table()
313 crop_and_interpolate(input_width, input_height, in prepare_shading_table()
/drivers/staging/media/ipu3/
A Dipu3-css-params.c54 if (input_width == output_width) { in imgu_css_scaler_setup_lut()
90 output_width / input_width; in imgu_css_scaler_setup_lut()
155 if (input_width == target_width) in imgu_css_scaler_calc()
167 input_width, target_width, in imgu_css_scaler_calc()
174 input_width, target_width, in imgu_css_scaler_calc()
294 unsigned int input_width; member
349 unsigned int input_width; member
444 (reso.input_width - in imgu_css_osys_calc_frame_and_stripe_params()
543 output_width = reso.input_width; in imgu_css_osys_calc_frame_and_stripe_params()
1007 osys->stripe[s].input_width = in imgu_css_osys_calc()
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A Dipu3-abi.h1038 u32 input_width; member
/drivers/gpu/drm/nouveau/include/dispnv04/i2c/
A Dsil164.h48 } input_width; member
/drivers/media/platform/verisilicon/
A Dhantro_postproc.c45 .input_width = {G1_REG_PP_INPUT_SIZE, 0, 0x1ff},
100 HANTRO_PP_REG_WRITE(vpu, input_width, MB_WIDTH(ctx->dst_fmt.width)); in hantro_postproc_g1_enable()
A Dhantro.h318 struct hantro_reg input_width; member
/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_display_cfg_types.h292 unsigned long input_width; member
/drivers/gpu/drm/nouveau/dispnv04/i2c/
A Dsil164_drv.c180 (config->input_width ? SIL164_CONTROL0_INPUT_24BIT : 0) | in sil164_init_state()
/drivers/media/platform/ti/omap3isp/
A Dispccdc.c140 unsigned int input_width, input_height; in ccdc_lsc_validate_config() local
164 input_width = format->width; in ccdc_lsc_validate_config()
169 min_width = ((input_width + lsc_cfg->initial_x + paxel_width - 1) in ccdc_lsc_validate_config()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_dcn4_calcs.c8562 …criptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_width, in dml_core_mode_support()

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